11

SCD5028-2 Rev G 5/7/2014

Aeroflex Plainview

REFERENCE CONDITIONING

Most resolvers have a LEADING input to output phase shift. A simple C-R leading phase shift network

(Figure 5 – Reference Conditioning) from the resolver reference to the RDC’s reference input will provide

the compensating phase shift required to bring the signals in phase. If the resolver has a LAGGING input to

output phase shift an R-C lagging phase shift network (low pass network) would be required.

Note the C-R phase lead circuit on the input to the Demodulator (BPF1 and BPF2) in Figure 1 should be

considered when calculating the total system phase compensation.

The formula for calculating the phase shift network is as follows:

1

Phase angle = ArcTan

6.28 x (R7 + R8) x C

Select a convenient capacitor value and perform the following calculation to determine the proper resistor

value.

R =

1

POWER UP INITIALIZATION

The RDC5028 RDC converter can provide incorrect data output if a unit step of 180° (starting at any

angle) is introduced to the Sin / Cos input.

This is difficult to reproduce since a Resolver will never provide a unit step function to the RDC chip.

The only time this would be a concern is during power up, if the Resolver is set to 180°. The RDC will

initialize its internal counter to 0000h which simulates the unit step function mentioned above. In

practice this error condition during power up is difficult to produce because of the dynamics associated

with all the variables when power is first applied.

If the system designer does nothing to accommodate this potential problem the system could see an

error at power on, however, this error will be self corrected once the Resolver begins to rotate. If the

Resolver does not rotate, the error can be corrected by writing to the RDC5028 any angle except 180°.

VELOCITY CONTROL

The RDC5028 RDC exhibits nonlinearity below 4 degrees/sec due to an anti-dither circuit that was

added to reduce the effects of any noise condition that may exist. This result can be seen in the least

significant bit or on the velocity output pins 9 & 10 on this device.