S2060 datasheet(3/22 Pages) AMCC

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S2060

GIGABIT ETHERNET TRANSCEIVER

March 7, 2001 / Revision H

TRANSMITTER DESCRIPTION

The S2060 transmitter accepts 10-bit parallel input

data and serializes it for transmission over fiber optic

or coaxial cable media. The chip is fully compatible

with the IEEE 802.3z Gigabit Ethernet standard, and

supports the Gigabit Ethernet data rate of 1250.0

Mbps. The S2060 uses a PLL to generate the serial

rate transmit clock. The transmitter runs at 10 times

the TBC input clock, and operates in either full rate

or half rate mode. At the full VCO rate the transmitter

runs at 1.25 GHz, while in half rate mode it operates

at 625 MHz.

Parallel-to-Serial Conversion

The parallel-to-serial converter takes in 10-bit wide

data from the input latch and converts it to a serial

data stream. Parallel data is latched into the trans-

mitter on the positive going edge of TBC. The data is

then clocked into the serial output shift register. The

shift register is clocked by the internally generated

bit clock which is 10x the TBC input frequency. TX[0]

is transmitted first.

Transmit Byte Clock (TBC)

The Transmit Byte Clock input (TBC) must be sup-

plied from a clock source with 100 ppm tolerance to

assure that the transmitted data meets the Gigabit

Ethernet frequency limits. The internal serial clock is

frequency locked to TBC (125.00 MHz).

TBC may be 62.5 MHz or 125 MHz, determined by

the state of the RATEN input. Operating rates are

shown in Table 2.

Transmit Latency

The average transmit latency is 4 byte times.

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Table 2. Operating Rates

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