S2060 datasheet(5/22 Pages) AMCC

Part #	S2060

Description	GIGABIT ETHERNET TRANSCEIVER

PDF	22 Pages

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Manufacturer	AMCC [Applied Micro Circuits Corporation]

Direct Link	http://www.amcc.com

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5 / 22 page

5

S2060

GIGABIT ETHERNET TRANSCEIVER

March 7, 2001 / Revision H

The COM_DET output signal is ACTIVE whenever

EN_CDET is active and the COMMA control charac-

ter is present on the RX[0:9] parallel data outputs.

The COM_DET output signal will be INACTIVE at all

other times.

Parallel Output Clock Rate and Data Stretching

The S2060 supports both full rate and half rate out-

puts, selected via the RATEN input. Table 4 shows

the operating rate scenarios. When RATEN is INAC-

TIVE, a data clock is provided on RBC1 at the data

rate. Data should be clocked on the rising edge of

RBC1. When RATEN is ACTIVE the device is in full

rate mode, and complementary TTL clocks are pro-

vided on the RBC0 and RBC1 outputs at 1/2 the

data rate as required by the Gigabit Ethernet Stan-

dard. Data is clocked on the rising edges of both

RBC0 and RBC1. See Figures 11 and 12.

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Table 4. Operating Rates

Fibre Channel and Gigabit Ethernet Standards re-

quire that the COMMA sync character appears on

the rising edge of the RBC1 signal. In full rate mode

the phase of the data is adjusted such that this re-

quirement is met. No alignment is necessary when

the S2060 is operating in half rate mode since the

output clock frequency is equal to the parallel word

rate (RATEN INACTIVE).

In ethernet applications it is illegal for multiple con-

secutive COMMA characters to be generated. How-

ever, multiple consecutive COMMA characters can

occur in serial backplane applications. The S2060 is

able to operate properly when multiple consecutive

COMMA characters are received: after the first

COMMA is detected and aligned, the RBC0/RBC1

clock operates without glitches or loss of cycles.

Additionally, COM_DET stays high while multiple

COMMAS are being output.

Receive Latency

The average receive latency is 8 byte times.

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