TMDS181I datasheet(8/58 Pages) TI1

8 / 58 page

TMDS181, TMDS181I

SLASE75A – AUGUST 2015 – REVISED OCTOBER 2015

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6.6 TMDS Differential Input Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX(2)

UNIT

DR_RX_DATA_R TMDS data lanes data rate

0.25

Gbps

(Retimer Mode)

DR_RX_DATA_R TMDS data lanes data rate

0.25

3.4

Gbps

(Redriver Mode)

DR_RX_CLK

TMDS clock lanes clock rate

340

MHz

tRX_DUTY

Input clock duty circle

40%

50%

60%

tCLK_JIT

Input clock jitter tolerance

0.3

Tbit

tDATA_JIT

Input data jitter tolerance

Test the TTP2, see Figure 12

150

Test at TTP2 when DR = 1.6 Gbps, see

tRX_INTRA

Input intrapair skew tolerance

112

Figure 12

tRX_INTER

Input interpair skew tolerance

1.8

Fixed EQ gain for data lane

EQ_SEL/A0 = H; fixed EQ gain, test at 6

EQH(D)

IN_D(0,1,2)n/p

Gbps

Fixed EQ gain for data lane

EQ_SEL/A0 = L; fixed EQ gain, test at 6

EQL(D)

7.5

IN_D(0,1,2)n/p

Gbps

Adaptive EQ gain for data lane

EQ_SEL/A0 = NC; adaptive EQ

EQZ(D)

IN_D(0,1,2)n/p

(Retimer Mode Only)

EQ(c)

EQ gain for clock lane IN_CLKn/p

EQ_SEL/A0 = H,L,NC

Input differential termination

RINT

100

115

Ω

impedance

VITERM

Input termination voltage

OE = H

3.3

3.465

(1)

The typical rating is simulated at 3.3 V VCC and 1.2 V VDD and at 27°C unless otherwise noted

(2)

The maximum rating is simulated at 3.465 V VCC and 1.27 V VDD and at 85°C unless otherwise noted

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