LXT972A datasheet(21/70 Pages) INTEL

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3.3V Dual-Speed Fast Ethernet Transceiver Datasheet — LXT972A

Datasheet

3.4

Initialization

When the LXT972A is first powered on, reset, or encounters a link failure state, it checks the

MDIO register configuration bits to determine the line speed and operating conditions to use for

the network link. The configuration bits may be set by the Hardware Control or MDIO interface as

shown in Figure 6.

3.4.1

MDIO Control Mode

In the MDIO Control mode, the LXT972A reads the Hardware Control Interface pins to set the

initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to

the MDIO interface.

3.4.2

Hardware Control Mode

In the Hardware Control Mode, LXT972A disables direct write operations to the MDIO registers

via the MDIO Interface. On power-up or hardware reset the LXT972A reads the Hardware Control

Interface pins and sets the MDIO registers accordingly.

The following modes are available using either Hardware Control or MDIO Control:

• Force network link operation to:

100TX, Full-Duplex.

100TX, Half-Duplex.

10BASE-T, Full-Duplex.

10BASE-T, Half-Duplex.

• Allow auto-negotiation / parallel-detection.

When the network link is forced to a specific configuration, the LXT972A immediately begins

operating the network interface as commanded. When auto-negotiation is enabled, the LXT972A

begins the auto-negotiation / parallel-detection operation.

LXT972A Datasheet(PDF) 21 Page - Intel Corporation