10

LM5109A

SNVS412B – APRIL 2006 – REVISED MARCH 2016

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9 Layout

9.1 Layout Guidelines

Optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations

during circuit board layout. The following points are emphasized:

1. Low ESR / ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB

and HS pins to support high peak currents being drawn from VDD and HB during the turn-on of the external

MOSFETs.

2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a

good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS).

3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between

the top MOSFET source and the of the bottom MOSFET drain (synchronous rectifier) must be minimized.

4. Grounding considerations:

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The first priority in designing grounding connections is to confine the high peak currents that charge and

discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and

minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close

as possible to the MOSFETs.

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The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap

diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The

bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground

referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak

current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.