C1

10 F

C4

0.1 F

C5

100 F

C2

0.1 F

C3

0.1 F

R2

26.7 k

R3

80.6 k

R4 100 k

R1 80.6 k

FAULTZ

V3P3

V3P3OUT

V3P3

V3P3

V3P3

V3P3OUT

FAULTZ

FAULTZ

FAULTZ

GND

GND

GND

GND

GND

GND

GND

OUT

OUT

OUT

GND

GND

GND

GND

GND

PAD

TPS22981RGPR

S0

S0

U1

VHV

VHV

HV_EN

EN

ENHVU

ISET_S0

ISET_S3

ISET_V3P3

HV_EN

EN

ENHVU

HV_EN

EN

ENHVU

1

2

3

13

15

21

20

19

18

4

5

16

11

9

10

14

12

8

17

6

7

S0

TPS22981

www.ti.com

SLVSBM6B – DECEMBER 2012 – REVISED NOVEMBER 2015

10 Layout

10.1 Layout Guidelines

•

Ensure decoupling capacitors on the OUT, V3P3, and V3P3OUT pins are tied directly to a solid ground plane

or ground connection, and are placed as close to each respective pin as possible.

•

Route the VHV input to minimize total inductance between the source for this power supply and the VHV pin.

See Input Inductive Bounce regarding inductance in the VHV input potentially causing damaging voltage

levels if large currents are suddenly turned off in the course of system operation.

•

Layout trace width should be checked to ensure adequate current carrying ability and suitable resistive

voltage drops in view of peak current levels.

Figure 10 shows the schematic used for the layout provided in the Layout Example section.

Figure 10. Layout Example Schematic

The TPS22981 can be placed on the same layer as its components. The layout can be a smaller area when the

bottom is used for component placement. In this design example, the components and the TPS22981 are placed

on the top layer. Figure 11 and Figure 12 show the suggested placement of the components.

For the nets V3P3, OUT, and VHV, TI recommends to use Thunderbolt three 8-mil or 16-mil vias when moving

from layer to layer. A 40-mil trace or pour will allow roughly 2 A to pass current carrying capability with 0.5-oz.

copper. Two 8-mil or 16-mil vias and 12-mil traces are sufficient for V3P3OUT. All of the other signals can be

routed using a 10-mil trace with an 8-mil or 16-mil via. Figure 13 and Figure 14 show the suggested power and

signal routing with and without a GND pour on the top layer. TI recommends that the capacitors and the GND

pad on the TPS22981 are connected on the same plane.

The remaining signals can be routed through the bottom layer or other internal layer. Figure 15 shows the bottom

routing.

Copyright © 2012–2015, Texas Instruments Incorporated

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