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PI6C20800SIVE Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6C20800SIVE Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 10 page ![]() 1 PS8887D 03/29/10 Features • PhasejitterfilterforPCIe®application • EightPairsofDifferentialClocks • Lowskew<50ps(PI6C20800S),<60ps(PI6C20800SI) • LowCycle-to-cyclejitter<50ps • OutputEnableforalloutputs • OutputsTristatecontrolviaSMBus • PowerManagementControl • ProgrammablePLLBandwidth • PLLorFanoutoperation • 3.3VOperation • IndustrialTemperatureOption-PI6C20800SI • Packaging(Pb-Free&Green): —48-PinSSOP(V) —48-PinTSSOP(A) PI6C20800S Description PI6C20800SisaPCIExpress®,high-speed,low-noisedifferential clock buffer designed to be a companion to PI6C410BS PCI Express clock generator for Intel server chipsets.The device distributesthedifferentialSRCclockfromPI6C410BStoeight differential pairs of clock outputs either with or without PLL. TheinputSRCclockcanbedividedby2whenSRC_DIV#is LOW.The clock outputs are controlled by input selection of SRC_STOP#,PWRDWN#andSMBus,SCLKandSDA.When inputofeitherSRC_STOP#orPWRDWN#isLOW,theoutput clocksareTristated.WhenPWRDWN# is LOW, theSDA and SCLKinputsmustbeTristated. Block Diagram PCI Express® 1:8 HCSL Clock Buffer Pin Configuration OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3# DIV Output Control SMBus Controller PLL PLL_BW# SRC SRC# PLL/BYPASS# SRC_DIV# SCLK SDA OE_INV OE [0:7] SRC_STOP# PWRDWN# OUT4 OUT4# OUT5 OUT5# OUT6 OUT6# OUT7 OUT7# LOCK VDD_A VSS_A IREF LOCK OE_7 OE_4 OUT7 OUT7# OE_INV VDD OUT6 OUT6# OE_6 OE_5 OUT5 OUT5# VSS VDD OUT4 OUT4# PLL_BW# SRC_STOP# PWRDWN# VSS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SRC_DIV# VDD VSS SRC SRC# OE_0 OE_3 OUT0 OUT0# VSS VDD OUT1 OUT1# OE_1 OE_2 OUT2 OUT2# VSS VDD OUT3 OUT3# PLL/BYPASS# SCLK SDA 10-0150 |
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