3

PS8887D

03/29/10

PI6C20800S

HCSL Clock Buffer

Data Byte 0: Control Register

Bit

Descriptions

Type

Power Up Condition

Output(s) Affected

Pin

0

SRC_DIV#

0=Divideby2

1=Normal

RW

1=x1

OUT[0:7],OUT[0:7]#

NA

1

PLL/BYPASS#

0=Fanout

1=PLL

RW

1=PLL

OUT[0:7],OUT[0:7]#

NA

2

PLLBandwidth

0=HIGHBandwidth,

1=LOWBandwidth

RW

1=Low

OUT[0:7],OUT[0:7]#

NA

3

RESERVED

4

RESERVED

5

RESERVED

6

SRC_STOP#

0=Drivenwhenstopped

1=Tristate

RW

0=Drivenwhenstopped

OUT[0:7],OUT[0:7]#

7

PWRDWN#

0=Drivenwhenstopped

1=Tristate

RW

0=Drivenwhenstopped

OUT[0:7],OUT[0:7]#

NA

Data Byte 1: Control Register

Bit

Descriptions

Type

Power Up Condition

Output(s) Affected

Pin

0

OUTPUTSenable

1=Enabled

0=Disabled

RW

1=Enabled

OUT0,OUT0#

NA

1

RW

1=Enabled

OUT1,OUT1#

NA

2

RW

1=Enabled

OUT2,OUT2#

NA

3

RW

1=Enabled

OUT3,OUT3#

NA

4

RW

1=Enabled

OUT4,OUT4#

NA

5

RW

1=Enabled

OUT5,OUT5#

NA

6

RW

1=Enabled

OUT6,OUT6#

NA

7

RW

1=Enabled

OUT7,OUT7#

NA

1bit

7bits

1

1

8bits

1

1

7bits

1

1

8bits

1

8bits

1

8bits

1

1bit

Start

bit

Slave

Addr

W

Ack Register

offset

Ack

Repeat

Start

Slave

Addr

R

Ack

Byte

Count

=N

Ack

Data

Byte

Offset

Ack

Data

Byte

N-1

Not

Ack

Stop

bit

Note:

2. Registeroffsetforindicatingthestartingregisterforindexedblockwriteandindexedblockread.

10-0150