3

www.pericom.com

P-0.1

02/29/12

PI6C49015

Embedded Clock Generator

Serial Data Interface (SMBus)

PI6C49015 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-

dress and read/write bit as shown below.

Address Assignment

A6

A5

A4

A3

A2

A1

A0

R/W

1

1

0

1

0

0

1

0/1

How to Write

1 bit

8 bits

1

8 bits

1

8 bits

1

8 bits

1

8 bits

1

1 bit

Start

bit

d2H

Ack

Register

offset

Ack

Byte

Count = N

Ack

Data Byte

0

Ack

…

Data Byte

N - 1

Ack

Stop

bit

Note:

1.

Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.

How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock)

1 bit

8

bits

1 bit

8

bits

1 bit

1 bit

8

bits

1 bit

8

bits

1 bit

8

bits

1 bit

…

8

bits

1 bit

1 bit

M:

Start

bit

M:

Send

"D2h"

S:

sends

Ack

M:

send

start-

ing

data-

byte

loca-

tion:

N

S:

sends

Ack

M:

Start

bit

M:

Send

"D3h"

S:

sends

Ack

S:

sends

# of

data

bytes

that

will

be

sent:

X

M:

sends

Ack

S:

sends

start-

ing

data

byte

N

M:

sends

Ack

…

S:

sends

data

byte

N+X-

1

M: Not

Ac-

knowl-

edge

M:

Stop

bit

Byte 0: Spread Spectrum Control Register

Bit

Description

Type

Power Up

Condition

Output(s)

Affected

Notes

7

Spread Spectrum Selection for 100 MHz HCSL

PCI-Express clocks

RW

0

All 100MHz HCSL

PCI Express output

0=spread off

1 = -0.5% down

spread

6

Enables hardware or software control of OE bits

(see Byte 0–Bit 6 and Bit 5 Functionality table)

RW

0

PD_RESET pin,

bit 5

0 = hardware cntl

1 = software ctrl

5

Software PD_RESET bit. Enables or disables all

outputs

(see Byte 0–Bit 6 and Bit 5 Functionality table)

RW

1

All outputs

0 = disabled

1 = enabled

4 to 1 Reserved

RW

Undefined

Not Applicable

0

OE for 25M_Out2

RW

1

25M_Out2

0 = disabled

1 = enabled

12-0168