6

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PI6C49018

Rev. A

12/10/2014

PI6C49018

Low Power Networking Clock Generator

Byte 1: Control Register

Bit

Description

Type

Power Up Condi-

tion

Output(s) Affected

Notes

7

OE for 80 MHz output

RW

1

80MHz

0 = disabled

1 = enabled

6 to 0

Reserved

R

-

-

-

Bit

Description

Type

Power Up Condi-

tion

Output(s) Affected

Notes

7 to 0

Reserved

R

-

-

-

Byte 2: Control Register

Byte 3: Spread Spectrum Control Register

Bit

Description

Type

Power Up

Condition

Output(s)

Affected

Notes

7

OE for 60MHz output

RW

0

60M

1 = enabled

0 = disabled

6

Reserved

R

-

-

-

5

OE for 100MHz HCSL

PCI-Express output PCIE3

RW

0

100MHz HCSL

PCI-Express output

PCIE3

1 = enabled

0 = disabled

4

OE for 100MHz HCSL

PCI-Express output PCIE2

RW

1

100MHz HCSL

PCI-Express output

PCIE2

1 = enabled

0 = disabled

3

Reserved

R

-

-

-

2

OE for 100MHz HCSL

PCI-Express output PCIE1

RW

1

100MHz HCSL

PCI-Express output

PCIE1

1 = enabled

0 = disabled

1

OE for 100MHz HCSL

PCI-Express output PCIE0

RW

1

100MHz HCSL

PCI-Express output

PCIE0

1 = enabled

0 = disabled

0

Reserved

R

-

-

-

Byte 0: Bit 6 and Bit 5 Functionality

Bit 6

Bit 5

Description

0

X

1

0

1

1

Enable outputs according to the SMBus default values; SMBus can control each output.

PD_RESET

HW pin/signal = DO NOT CARE

14-0209