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TLC59581 Datasheet(PDF) 16 Page - Texas Instruments |
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TLC59581 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 28 page ![]() GS Counter Line read counter and Sub-period counter ES-PWM Decoder and timing control for 48CH VCC SIN 48-bit Common shift register 48-CH Constant Current Sink 3-bit BC and 27-bit CC OUTR0 VCC LED Open Detection (LOD) OUTR1 GND 0 MSB LSB 47 SCLK LAT SOUT OUTG0 OUTG15 OUTB0 OUTB15 Power save control To all analog circuit 48 2 IREF IREFGND Thermal Pad Reference current control 48 Programmable Group delay Detection Voltage 48 48 Vsync 48kbit SRAM BANK A 16-bit x48CH x 32/16 Line BANK B 16-bit x48CH Line address for read 48-bit LOD data Command Decoder WRTGS BANK_SEL WRTFC READFC1/2 READSID 48 30 1 48 Vsync Vsync Address decoder and writing control 43 44-bit FC1 register 44-bit FC2 register x 32/16 Line TLC59581, TLC59582 SLVSCZ9A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 9.2 Functional Block Diagram 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated TLC59582 |
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