Functional Description

Multiplexer: The device contains a 16-channel single-ended

analog signal multiplexer. A particular input channel is se-

lected by using the address decoder.

Table 1 shows the input

states for the address line and the expansion control line to

select any channel. The address is latched into the decoder

on the low-to-high transition of the address latch enable

signal.

TABLE 1.

Selected

Address Line

Expansion

Analog Channel

DCBA

Control

IN0

LLLL

H

IN1

L

L

L

H

H

IN2

L

L

H

L

H

IN3

L

L

H

H

H

IN4

L

H

L

L

H

IN5

LHLH

H

IN6

LH

HL

H

IN7

L

H

H

H

H

IN8

H

L

L

L

H

IN9

HL

LH

H

IN10

HLHL

H

IN11

H

L

H

H

H

IN12

H

H

L

L

H

IN13

H

H

L

H

H

IN14

H

H

H

L

H

IN15

HHHH

H

All Channels OFF

XXXX

L

X=don’t care

Additional single-ended analog signals can be multiplexed to

the A/D converter by disabling all the multiplexer inputs using

the expansion control. The additional external signals are

connected to the comparator input and the device ground.

Additional signal conditioning (i.e., prescaling, sample and

hold, instrumentation amplification, etc.) may also be added

between the analog input signal and the comparator input.

CONVERTER CHARACTERISTICS

The Converter

The heart of this single chip data acquisition system is its

8-bit analog-to-digital converter. The converter is designed to

give fast, accurate, and repeatable conversions over a wide

range of temperatures. The converter is partitioned into 3

major sections: the 256R ladder network, the successive

approximation register, and the comparator. The converter’s

digital outputs are positive true.

The 256R ladder network approach

Figure 1 was chosen

over the conventional R/2R ladder because of its inherent

monotonicity, which guarantees no missing digital codes.

Monotonicity is particularly important in closed loop feedback

control systems. A non-monotonic relationship can cause

oscillations that will be catastrophic for the system. Addition-

ally, the 256R network does not cause load variations on the

reference voltage.

The bottom resistor and the top resistor of the ladder net-

work in

Figure 1 are not the same value as the remainder of

the network. The difference in these resistors causes the

output characteristic to be symmetrical with the zero and

full-scale points of the transfer curve. The first output transi-

and succeeding output transitions occur every 1 LSB later up

to full-scale.

DS005277-2

FIGURE 1. Resistor Ladder and Switch Tree

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