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PI6LC48P02 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation

Part # PI6LC48P02
Description  2-Output LVPECL Fibre Channel (FC) and Ethernet Clock Generator
PDF  11 Pages
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Manufacturer  PERICOM [Pericom Semiconductor Corporation]
Direct Link  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI6LC48P02 Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation

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www.pericom.com
PI6LC48P02
Rev. C
08/13/15
PI6LC48P02
Block Diagram
Description
The PI6LC48P02 is a 2-output LVPECL synthesizer optimized
to generate Fibre Channel, Ethernet and storage reference clock
frequencies and is a member of Pericom’s HiFlex family of high
performance clock solutions. Using a 26.5625MHz crystal, the
most popular Fibre Channel (FC) frequencies can be generated
based on the settings of 2 frequency select pins. Using 25MHz
Xtal, most Ethenrnet frequencies inckuding 100MHz can be
generated, while using 26.041667MHz Xtal, 156.25MHz can be
generated for Networking applications.
The PI6LC48P02 uses Pericom’s proprietary low phase noise
PLL technology to achieve ultra low phase jitter, it is ideal for
Networking, data center, and storage systems.
Applications
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Networking and Data Center Server systems
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Fibre Channel (FC) and Storage systems
Features
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Two differential LVPECL output pairs
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Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended clock input
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Supports the following output frequencies:
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Ethernet: 50MHz, 100MHz, 150MHz, 156.25MHz,
200MHz
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Fibre Channel: 53.125MHz, 106.25MHz, 159.375MHz,
187.5MHz, 212.5MHz
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RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(12kHz – 20MHz): 0.28ps (typical)
Î
Î
RMS phase jitter @ 100MHz, using a 25MHz crystal (12kHz
– 20MHz): 0.32ps (typical)
Î
Î
RMS phase jitter @ 156.25MHz, using a 26.041667MHz
crystal (12kHz – 20MHz): 0.30ps (typical)
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Full 3.3V or 2.5V supply modes
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Industrial operating temperature
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Available in lead-free package: 20-TSSOP
2-Output LVPECL Fibre Channel (FC) and Ethernet Clock Generator
PFD
VCO
M
OSC
XTAL_OUT
XTAL_IN
Ref_IN
IN_SEL
PLL_ByPass
/N
M_reset
N_SEL[0:1]
CLK0
CLK0#
CLK1
CLK1#
15-0102


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