LP5562TMXSLASHNOPB datasheet(28/52 Pages) TI1

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start

MSB

Chip id

LSB

ack

MSB Register Addr LSB

ack

MSB

Data

LSB

ack

stop

ack from slave

SCL

SDA

start

id = 011 0000b

ack

address = 02H

ack

address 02H data

stop

SVA-30197414

LP5562

SNVS820A – APRIL 2013 – REVISED SEPTEMBER 2015

www.ti.com

•

Slave sends acknowledge signal.

•

If master will send further data bytes the control register address will be incremented by one after

acknowledge signal.

•

Write cycle ends when the master creates stop condition.

7.5.2.7 Control Register Read Cycle

•

Master device generates a start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master device generates repeated start condition.

•

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

•

Slave sends acknowledge signal if the slave address is correct.

•

Slave sends data byte from addressed register.

•

If the master device sends acknowledge signal, the control register address will be incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

Table 25. I2C Data Read/Write Flow(1)

ADDRESS MODE

<Slave Address><r/w = 0>[Ack]

<Register Addr.>[Ack]

Data Read

<Slave Address><r/w = 1>[Ack]

[Register Data]<Ack or NAck>

... additional reads from subsequent register address possible

<Slave Address><r/w='0'>[Ack]

<Register Addr.>[Ack]

Data Write

<Register Data>[Ack]

... additional writes to subsequent register address possible

(1)

<>Data from master [] Data from slave

7.5.2.8 Register Read/Write Format

Figure 24. Register Write Format

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