TMS320C6743CPTP2 datasheet(4/151 Pages) TI1

4 / 151 page

Switched Central Resource (SCR)

BOOT ROM

32KB

L1 RAM

32KB

L1 Pgm

AET

C674x

DSP CPU

DSP Subsystem

JTAG Interface

System Control

Input

Clock(s)

Power/Sleep

Controller

Multiplexing

PLL/Clock

Generator

w/OSC

General-

Purpose

Timer

General-

Purpose

Timer

(Watchdog)

Serial Interfaces

I C

(2)

SPI

(1)

UART

(2)

Audio Ports

McASP

w/FIFO

(2)

DMA

Peripherals

External Memory Interfaces

Connectivity

EDMA3

Control Timers

ePWM

(3)

eCAP

(3)

eQEP

(2)

(10/100)

EMAC

(RMII)

MDIO

MMC/SD

(8b)

EMIFA(8b)

NAND/Flash

EMIFB

SDRAM Only

(16b)

GPIO

Memory

Protection

PRU

Subsystem

TMS320C6743

SPRS565D – APRIL 2009 – REVISED JUNE 2014

www.ti.com

1.4

Functional Block Diagram

Figure 1-1 shows the functional block diagram of the TMS320C6743 device.

(1)

Not all peripherals are available at the same time due to multiplexing.

Figure 1-1. TMS320C6743 Functional Block Diagram

TMS320C6743 Fixed- and Floating-Point Digital Signal Processor

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