ADC12062EVAL datasheet(12/20 Pages) NSC

12 / 20 page

Applications Information (Continued)

THE ANALOG INPUT

The analog input of the ADC12762 can be modeled as two

small resistances in series with the capacitance of the input

hold capacitor (C

IN), as shown in Figure 7. The S/H switch is

closed during the Sample period, and open during Hold. The

source has to charge C

IN to the input voltage within the

sample period. Note that the source impedance of the input

voltage (R

SOURCE) has a direct effect on the time it takes to

charge C

IN.IfRSOURCE is too large, the voltage across CIN

will not settle to within 0.5 LSBs of V

SOURCE before the con-

version begins, and the conversion results will be incorrect.

From a dynamic performance viewpoint, the combination of

SOURCE,RMUX,RSW, and CIN form a low pass filter. Mini-

mizing R

SOURCE will increase the frequency response of the

input stage of the converter.

Typical values for the components shown in

Figure 7 are:

MUX = 100Ω,RSW = 100Ω, and CIN = 25 pF. The settling

time to n bits is:

SETTLE = (RSOURCE +RMUX +RSW) * CIN * n * ln (2).

The bandwidth of the input circuit is:

−3dB = 1/(2 * 3.14 * (RSOURCE +RMUX +RSW) * CIN)

The ADC12762 is operated in a pipelined sequence, with

one hold capacitor acquiring the next sample while a conver-

sion is being performed on the voltage stored on the other

hold capacitor. This gives the source over t

CONV seconds to

charge the hold capacitor to its final value. At 1.4 MHz, the

settling time must be less than 714 ns. Using the settling

time equation and component values given, the maximum

source impedance that will allow the input to settle to 1⁄2 LSB

(n = 13) at full speed is

∼3kΩ. To ensure 1⁄2 LSB settling over

temperature

and

device-to-device

variation,

SOURCE

should be a maximum of 500

Ω when the converter is oper-

ated at full speed.

If the signal source has a high output impedance, its output

should be buffered with an operational amplifier capable of

driving a switched 25 pF/100

Ω load. Any ringing or instabili-

ties at the op amp’s output during the sampling period can

result in conversion errors. The LM6361 high speed op amp

is a good choice for this application due to its speed and its

ability to drive large capacitive loads.

Figure 8 shows the

LM6361 driving the ADC IN input of an ADC12762. The

100 pF capacitor at the input of the converter absorbs some

of the high frequency transients generated by the S/H

DS012811-28

FIGURE 5. The Capacitive Voltage Divider

DS012811-29

FIGURE 6. ADC Control Logic

ADC12062EVAL Datasheet(PDF) 12 Page - National Semiconductor (TI)

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