ADC12062EVAL datasheet(14/20 Pages) NSC

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Applications Information (Continued)

ANALOG MULTIPLEXER

The ADC12762 has an input multiplexer that is controlled by

the logic level on pin S0 when EOC goes low, as shown in

Figure 1 and Figure 2. Multiplexer setup and hold times with

respect to the S/H input can be determined by these two

equations:

MS (wrt S/H) = tMS −tEOC (min) = 50−60 = −10 ns

MH (wrt S/H) = tMH +tEOC (max) = 50 + 125 = 175 ns

Note that t

MS (wrt S/H) is a negative number; this indicates that

the data on S0 must become valid within 10 ns after S/H

goes low in order to meet the setup time requirements. S0

must be valid for a length of

MH +tEOC (max))−(tMS −tEOC (min)) = 185 ns.

Table 1 shows how the input channels are assigned:

TABLE 1. ADC12762 Input

Multiplexer Programming

Channel

IN1

IN2

The output of the multiplexer is available to the user via the

MUX OUT pin. This output allows the user to perform addi-

tional signal processing, such as filtering or gain, before the

signal is returned to the ADC IN input and digitized. If no ad-

ditional signal processing is required, the MUX OUT pin

should be tied directly to the ADC IN pin.

See Section 9.0 (APPLICATIONS) for a simple circuit that

will alternate between the two inputs while converting at full

speed.

REFERENCE INPUTS

In addition to the fully differential V

REF+ and VREF− reference

inputs used on most National Semiconductor ADCs, the

ADC12762 has two sense outputs for precision control of the

ladder voltage. These sense inputs compensate for errors

due to IR drops between the reference source and the ladder

itself. The resistance of the reference ladder may be 750

Ω.

The parasitic resistance (R

P) of the package leads, bond

wires, PCB traces, etc. can easily be 0.5

Ω to 1.0Ω or more.

This may not be significant at 8-bit or 10-bit resolutions, but

at 12 bits it can introduce voltage drops causing offset and

gain errors as large as 6 LSBs.

The ADC12762 provides a means to eliminate this error by

bringing out two additional pins that sense the exact voltage

at the top and bottom of the ladder. With the addition of two

op amps, the voltages on these internal nodes can be forced

to the exact value desired, as shown in

Figure 10.

DS012811-32

FIGURE 9. Input Protection

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