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MB9B210T Datasheet(PDF) 89 Page - SPANSION |
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MB9B210T Datasheet(HTML) 89 Page - SPANSION |
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89 / 137 page ![]() D a t a S h e e t 86 MB9B210T-DS706-00015-3v0-E, February 10, 2015 CONFIDENTIAL (7) External Bus Timing External bus clock output characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max Output frequency tCYCLE MCLKOUT* 1 Vcc ≥ 4.5 V - 50* 2 MHz Vcc < 4.5 V - 32* 3 MHz *1: External bus clock (MCLKOUT) is divided clock of HCLK. For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3 Family PERIPHERAL MANUAL". When external bus clock is not output, this characteristic does not give any effect on external bus operation. *2: When AHB bus clock frequency is more than 100 MHz, the divider setting for MCLKOUT must be more than 4. *3: When AHB bus clock frequency is more than 64 MHz, the divider setting for MCLKOUT must be more than 4. External bus signal input/output characteristics (Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics VIH - 0.8 × VCC V VIL 0.2 × VCC V Signal output characteristics VOH 0.8 × VCC V VOL 0.2 × VCC V VIH VIL VIL VIH VOH VOL VOL VOH Input signal Output signal MCLKOUT |
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