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MB9B500B Datasheet(PDF) 91 Page - SPANSION |
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MB9B500B Datasheet(HTML) 91 Page - SPANSION |
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91 / 113 page  D a t a S h e e t 88 MB9B500B-DS706-00021-3v0-E, December 15, 2014 CONFIDENTIAL 5. 12bit A/D Converter · Electrical characteristics for the A/D converter. (Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40C to + 85C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - - ± 2 ± 4.5 LSB AVRH = 2.7V to 5.5V Differential Nonlinearity - - - ± 2 ± 2.5 LSB Zero transition voltage VZT ANxx - ± 5 ± 20 mV Full-scale transition voltage VFST ANxx - AVRH ± 10 AVRH ± 20 mV Conversion time - - 1.0* 1 - - μs AVcc ≥ 4.5V 2.666* 1 - - AVcc < 4.5V Sampling time Ts - *2 - - ns AVcc ≥ 4.5V *2 - - AVcc < 4.5V Compare clock cycle *3 Tcck - 55.5 - 10000 ns AVcc ≥ 4.5V 166.6* 4 AVcc < 4.5V State transition time to operation permission Tstt - - - 2.5 μs Analog input capacity CAIN - - - 14.5 pF Analog input resistance RAIN - - - 0.93 kΩ AVcc ≥ 4.5V 2.04 AVcc < 4.5V Interchannel disparity - - - - 4 LSB Analog port input current - ANxx - - 5 μA Analog input voltage - ANxx AVSS - AVRH V Reference voltage - AVRH 2.7 - AVCC V *1: The Conversion time is the value of sampling time(Ts) + compare time(Tc). The condition of the minimum conversion time is the following. AVcc ≥ 4.5V, HCLK=72MHz sampling time: 0.222μs compare time: 0.778μs AVcc < 4.5V, HCLK=54MHz sampling time: 0.333μs compare time: 2.333μs Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck). For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3 Family PERIPHERAL MANUAL Analog Macro Part". The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock timing. The sampling clock and compare clock is generated from the Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see "BLOCK DIAGRAM" in this data sheet. *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1) *3: The Compare time (Tc) is the value of (Equation 2) *4: When 12bit A/D converter is used at AVcc<4.5V, there is a limitation as follows. Please set the HCLK frequency under 54MHz. |
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