2

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P-0.3

12/12/12

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PI3PCIE3422

3.3V, PCI Express® 3.0 2-Lane, Differential Mux/Demux with Bypass

Pin Description

Pin #

Pin Name I/O Description

1

2

A0+

A0–

I/O

Signal I/O, Channel 0, Port A

5

6

A1+

A1–

I/O

Signal I/O, Channel 1, Port A

10

11

A2+

A2–

I/O

Signal I/O, Channel 2, Port A

14

15

A3+

A3–

I/O

Signal I/O, Channel 3, Port A

38

37

B0+

B0−

I/O

Signal I/O, Channel 0, Port B

34

33

B1+

B1−

I/O

Signal I/O, Channel 1, Port B

29

28

B2+

B2−

I/O

Signal I/O, Channel 2, Port B

25

24

B3+

B3−

I/O

Signal I/O, Channel 3, Port B

3

4

C0+

C0–

I/O

Signal I/O, Channel 0, Port C

7

8

C1+

C1–

I/O

Signal I/O, Channel 1, Port C

12

13

C2+

C2–

I/O

Signal I/O, Channel 2, Port C

16

17

C3+

C3−

I/O

Signal I/O, Channel 3, Port C

36

35

D0+

D0−

I/O

Signal I/O, Channel 0, Port D

32

31

D1+

D1−

I/O

Signal I/O, Channel 1, Port D

27

26

D2+

D2−

I/O

Signal I/O, Channel 2, Port D

23

22

D3+

D3−

I/O

Signal I/O, Channel 3, Port D

41

OE#

I

Output Enable, active low. When OE# = 0 the device I/O is enabled. When OE#=1,

all I/O are high impedance

9

SEL

I

Operation mode Select

(when SEL=0: A→B, C→D, when SEL=1: A→D, B + C = Hi-Z)

18, 20, 30, 40, 42

Pwr 3.3V ±10% Positive Supply Voltage

19, 21, 39, Center Pad GND

Pwr Power ground

13-0011