AD7761BSTZ datasheet(39/69 Pages) AD

39 / 69 page

Data Sheet

AD7761

Rev. 0 | Page 39 of 69

ANALOG INPUTS

Figure 58 shows the AD7761 analog front end. The ESD

protection diodes that are designed to protect the ADC from

some short duration overvoltage and ESD events are shown on

the signal path. The analog input is sampled at twice the

modulator sampling frequency, fMOD, which is derived from

MCLK. By default, the ADC internal sampling capacitors, CS1

and CS2, are driven by a per channel analog input precharge

buffer to ease the driving requirement of the external network.

BPS 0+

AVDD1

AIN0+

CS2

PHI 0

PHI 1

PHI 0

CS1

AIN0–

AVSS

AVDD1

BPS 0–

Figure 58. Analog Front End

The analog input precharge buffers provide the initial approximate

charging of the switched capacitor network for 25% of the sampling

phase. During this first phase, the bypass switches, BPS 0+ and

BPS 0−, remain open. For the remaining 75% of the sampling

phase, the bypass switches are closed, and the fine accuracy

settling charge is provided by the external source. PHI 0 and PHI 1

represent the modulator clock sampling phases that switch the

input signals onto the sampling capacitors, CS1 and CS2.

The analog input precharge buffers reduce the switching kickback

from the sampling stage to the external circuitry. The precharge

buffer reduces the average input current by a factor of eight, and

makes the input current more signal independent, to reduce the

effects of sampling distortion. This reduction in drive requirements

allows pairing of the AD7761 with lower power, lower bandwidth

front-end driver amplifiers such as the ADA4940-1/ADA4940-2.

–400

–300

–200

–100

100

200

300

400

23456

INPUT VOLTAGE (VDIFF)

UNBUFFERED AINx+

UNBUFFERED AINx–

Figure 59. Analog Input Current (AIN) vs. Input Voltage, Analog Input

Precharge Buffer Off, VCM = 2.5 V, fMOD = 8.192 MHz

–30

–25

–20

–15

–10

–5

01234

INPUT VOLTAGE (VDIFF)

PRECHARGE BUFFERED AINx+

PRECHARGE BUFFERED AINx–

Figure 60. Analog Input Current (AIN) vs. Input Voltage, Analog Input

Precharge Buffer On, VCM = 2.5 V, fMOD = 8.192 MHz

The analog input precharge buffers can be turned on/off by means

of a register write to Register 0x11 and Register 0x12 (Precharge

Buffer Register 1 and Precharge Buffer Register 2, respectively).

Each analog input precharge buffer is selectable per channel. In

pin control mode, the analog input precharge buffers are always

enabled for optimum performance.

When the analog input precharge buffers are disabled, the

analog input current is sourced completely from the analog

input source. The unbuffered analog input current is calculated

from two components: the differential input voltage on the

analog input pair, and the analog input voltage with respect to

AVSS. With the precharge buffers disabled, for 32.768 MHz

MCLK in fast mode with fMOD = MCLK/4, the differential input

current is approximately 48 μA/V and the current with respect

to ground is approximately 17 μA/V.

For example, if the precharge buffers are off, with AIN1+ = 5 V,

and AIN1− = 0 V, estimate the current in each input pin as

follows:

AIN1+ = 5 V × 48 μA/V + 5 V × 17 μA/V = 325 μA

AIN1− = −5 V × 48 μA/V + 0 V × 17 μA/V = −240 μA

When the precharge buffers are enabled, the absolute voltage with

respect to AVSS determines the majority of the current. The

maximum input current of approximately −25 μA is measured

when the analog input is close to either the AVDD1 or AVSS rails.

With either precharge buffers enabled or disabled, the analog

input current scales linearly with the modulator clock rate. The

analog input current vs. input voltage is shown in Figure 59.

Full settling of the analog inputs to the ADC requires the use of an

external amplifier. Pair amplifiers such as the ADA4805-2 for focus

mode, the ADA4805-2 or ADA4940-1/ADA4940-2 for median

mode, and the ADA4807-2 or ADA4896-2 for fast mode with the

AD7761 (see Table 24 for details on some of these pairings.).

Running the AD7761 in median and focus modes or reducing

the MCLK rate reduces the load and speed requirements of the

amplifier; therefore, lower power amplifiers can be paired with

the analog inputs to achieve the optimum signal chain efficiency.

AD7761BSTZ Datasheet(PDF) 39 Page - Analog Devices

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