AD7761BSTZ datasheet(43/69 Pages) AD

43 / 69 page

Data Sheet

AD7761

Rev. 0 | Page 43 of 69

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fCHOP = fMOD/32

fCHOP = fMOD/8

fIN/fMOD

Figure 65. Rejection of Out of Band Input Tones, Wideband Filter,

Decimation = ×32, fMOD = 8.192 MHz, Analog Input Sweep from DC to 20 MHz

Modulator Chopping Frequency

Figure 65 plots two scenarios that relate to the chopping frequency

of the AD7761 modulator.

The AD7761 uses a chopping technique in the modulator similar

to that of a chopped amplifier to remove offset, offset drift, and

1/f noise. The AD7761 default chopping rate is fMOD/32. In pin

control mode, the chop frequency is hardwired to fMOD/32. In

SPI control mode, the user can select the chop frequency to be

either fMOD/32 or fMOD/8.

As shown in Figure 65, the stop band rejection of the digital filter is

reduced at frequencies that relate to even multiples of the chopping

frequency (fCHOP). All other out of band frequencies (excluding

those already discussed relating to the modulator clock frequency,

fMOD) are rejected by the stop band attenuation of the digital filter.

An out of band tone with a frequency in the range of (2 × fCHOP ) ±

f3dB, where f3dB is the filter bandwidth employed, is attenuated to

the envelope determined by the chop frequency setting (see

Figure 65), and aliased into the pass band. Out of band tones near

additional even multiples of fCHOP (that is, N × fCHOP, where N is

an even integer), are attenuated and aliased in the same way.

Chopping at fMOD/32 offers the best performance for noise,

offset, and offset drift for the AD7761.

For ac performance it may be useful to select chopping at fMOD/8

as this moves the first chopping tone to a higher frequency.

However, chopping at fMOD/8 may lead to slightly degraded

noise (approximately 1 dB loss in dynamic range) and offset

performance compared to the default chop rate of fMOD/32.

Table 26 shows the aliasing achieved by different order

antialiasing filter options at the critical frequencies of fMOD/32

and fMOD/8 for chop aliasing, fMOD/16 for modulator saturation,

and 2 × fMOD for the first zone with 0 dB attenuation. It assumes

the corner frequency of the antialiasing filter is at fMOD/64,

which is just above the maximum input bandwidth that the

AD7761 digital filter can pass when using a decimate by 32 filter

setting.

Table 26. External Antialiasing Filter Attenuation

RC Filter

fMOD/32

(dB)

fMOD/16

(dB)

fMOD/8

(dB)

2 × fMOD

(dB)

First Order

−6

−12

−18

−42

Second Order

−12

−24

−36

−84

Third Order

−18

−36

−54

−126

Modulator Saturation Point

A Σ-Δ modulator can be considered a standard control loop,

employing negative feedback. The control loop works to ensure

that the average processed error signal is very small over time. It

uses an integrator to remember preceding errors and force the

mean error to be zero. As the input signal rate of change increases

with respect to the modulator clock, fMOD, a larger voltage feedback

error is processed. Above a certain frequency, the error begins

to saturate the modulator.

For the AD7761, the modulator may saturate for full-scale input

frequencies greater than fMOD/16, depending on the rate of change

of input signal, input signal amplitude, and reference input level.

A half power input tone at fMOD/8 also causes the modulator to

saturate. In applications where there may be high amplitude and

frequency out of band tones, a first-order antialiasing filter is

required with a −3 dB corner frequency set at fMOD/16 to protect

against modulator saturation. For example, if operating the

AD7761 at full speed and using a decimation rate of ×32 to achieve

an output data rate of 256 kSPS, the modulator rate is equal to

8.192 MHz. In this instance, to protect against saturation, set the

antialiasing filter −3 dB corner frequency to 512 kHz.

CALIBRATION

In SPI control mode, the AD7761 offers users the ability to adjust

offset, gain, and phase delay on a per channel basis.

Offset Adjustment

The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_

OFFSET_LSB registers are 24 bit, signed twos complement

registers for channel offset adjustment. If the channel gain setting is

at its ideal nominal value of 0x555555, an LSB of offset register

adjustment changes the digital output by −1/192 LSBs. For

example, changing the offset register from 0 to 4800 changes the

digital output by −25 LSBs. Because offset calibration occurs

before gain calibration, the ratio of 1/192 changes linearly with

gain adjustment via the Channel x gain registers (see Table 53).

After a reset or power cycle, the offset register values revert to

the default factory setting.

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