CLC014 datasheet(11/18 Pages) NSC

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Layout and Measurement

The printed circuit board layout for the CLC014 requires

proper high-speed layout to achieve the performance speci-

fications found in the datasheet. The following list contains a

few rules to follow:

Use a ground plane.

Decouple power pins with 0.1 µF capacitors placed

≤ 0.1” (3mm) from the power pins.

Design transmission strip lines from the CLC014’s input

and output pins to the board connectors.

Route outputs away from inputs.

Keep ground plane

≥ 0.025” (0.06mm) away from the in-

put and output pads.

Figure 8 shows a block level measurement diagram, while

Figure 15 on depicts a detailed schematic. A pseudo-random

pattern generator with low output jitter was used to provide a

NRZI pattern to create the eye diagrams shown in the

Typi-

cal Performance Characteristics section.

Since most pattern generators have a 50

Ω output imped-

ance, a translation can be accomplished using a CLC006

Cable Driver as an impedance transformer. A wide band-

width oscilloscope is needed to observe the high data rate

eye pattern. When monitoring a single output that is termi-

nated at both the equalizer output and the oscilloscope, the

effective output load is 37.5

Ω. Consequently, the signal

swing is half that observed for a single-ended 75

Ω

termination.

Troubleshooting with scope probes can affect the equaliza-

tion. For high data rates, use a

low capacitance probe with

less than 2 pF probe capacitance. Evaluation boards and lit-

erature are available for quick prototyping and evaluation of

the CLC014 Adaptive Cable Equalizer. The CLC014 con-

tains CMOS devices and operators should

use grounding

straps when handling the parts.

Figure 9 shows the CLC014’s internal power supply routing.

Bypass V

CC (pin 4) by:

•

Monolithic capacitor of about 0.1 µF placed less than 0.1”

(3mm) from the pin

•

Tantalum capacitor of about 6.8 µF for large current sig-

nal swings placed as close as convenient to the CLC014

To minimize ringing at the CLC014’s inputs, place a 100

Ω re-

sistor in series with the input. This resistor reduces induc-

tance effects.

Several layout techniques can improve high speed perfor-

mance:

•

Keep input, output and AEC traces well separated

•

Use balanced input termination’s

•

Avoid routing traces close to the CLC014’s input trace

DS100056-28

FIGURE 8. Typical Measurement Block

DS100056-29

FIGURE 9. Power Package Routing Fixture

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