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CLC018 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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CLC018 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 18 page ![]() Electrical Characteristics (Continued) (V CC = 0V, VEE = −5V, VLL = 0V; unless otherwise specified) (Note 4). Parameter Conditions Typ +25˚C Min/Max +25˚C Min/Max −40˚C to +85˚C Units Signal I/O: Output Voltage Swing R LOAD =75Ω 800 640/960 540/1060 mV Output Voltage Range Lower Limit −2.5 V Output Voltage Range Upper Limit 0 V Control Inputs: Input Voltage - HIGH V IH min (Note 3) −1 −0.5 −0.5 V Input Voltage - LOW V IL max (Note 3) −4 −4.5 −4.5 V Input Voltage - HIGH V IH min V LL = +5V (Note 3) 4 4.5 4.5 V Input Voltage - LOW V IL max V LL = +5V (Note 3) 1 0.5 0.5 V Input Current - HIGH V IH =VLL (Note 3) 1 0.2/2.0 0.1/2.5 µA Input Current - LOW V IL =VLL −5V (Note 3) −100 −200/10 −250/15 µA MISCELLANEOUS PERFORMANCE V CC Supply Current All Outputs Active (Notes 3, 13, 14) 157 127/202 119/217 mA V CC Supply Current All Outputs TRI-STATE (Note 3) 7 3/11 2/12 mA V LL Supply Current V LL = 0V (Note 3) 2.5 1.7/3.3 1.5/3.5 mA V LL Supply Current V LL = +5V (Note 3) 7 mA Input Capacitance 1.5 pF Output Capacitance 2 pF Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: J-level spec. is 100% tested at +25˚C. Note 4: VLL and all VEE supply pins are bypassed with 0.01 µF ceramic capacitor. Note 5: Bit error rate less than 10−9 over 50% of the bit cell interval. Note 6: Measured using a pseudo-random (223−1 pattern) binary sequence with all other channels active with an uncorrelated signal. Note 7: Spread in propagation delays for all input/output combinations. Note 8: Measured between the 20% and 80% levels of the waveform. Note 9: Difference in propagation delay for output low-to-high vs. output high-to-low transition. Note 10: Refer to the Configuration Timing Diagram. Note 11: Refer to the Reset Timing Diagram. Note 12: The bias current for high speed data input depends on the number of data outputs that are selecting that input. Note 13: The VCC supply current is a function of the number of active data outputs. IVCC 18*N+7mA where N is an integer from 0 to 8. Note 14: IVEE =IVCC +IVLL. www.national.com 3 |
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