CLC018 datasheet(8/18 Pages) NSC

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Operation (Continued)

the range is best. For ECL signals this point is about 2 diode

drops below ground. It is possible to bias the unused input

with a low-pass filtered version of the data, as shown in

Fig-

ure 5. In some coding schemes there are pathological pat-

terns that result in long sequences with no data transitions.

During these patterns, the bias on the unused input will drift

towards the other input reducing the noise immunity which

makes this scheme undesirable. The most robust solution for

single ended inputs is to place a comparator with hysteresis

in front of the CLC018. Such a part is the MC10E1652. See

Figure 6 for an example of how to hook this up.

OUTPUT INTERFACING

The outputs of the CLC018 are differential, current source

outputs. They can be converted to ECL compatible levels

with the use of resistive loads as shown in

Figure 7. The out-

put swings will have a similar temperature coefficient to

10KECL if a 1N4148 diode is used to set V

OH. For most com-

mercial temperature range applications, a 75

Ω resistor can

be used as shown in

Figure 8. Many circuits with differential

inputs, such as the CLC016 Data Retimer With Automatic

Rate Selection, do not require true ECL levels, so the load

resistors can be connected directly to the positive rail as

shown in

Figure 9.

POWER SUPPLIES, GROUNDING AND BYPASSING

The CLC018 uses separate power supplies for control and

data circuitry. Data circuitry is supplied via V

CC and control

circuitry via V

LL. Supply connection VEE, the negative-most

supply, is the common return for both. Connection details for

the different powering modes is shown in

Table 1.

Internal and external capacitances, normal and parasitic,

must be charged and discharged with changes in output volt-

age. Charging current depends upon the size of these ca-

pacitances and the rate of change of voltage. At the fast tran-

sition times of the CLC016, small amounts of stray

capacitance at outputs can produce large output and supply

transient currents. Controlling transient currents requires

particular attention to minimizing stray capacitances and to

providing effective bypassing in the design. Good and effec-

tive bypassing consisting of 0.01 µF to 0.1 µF monolithic ce-

ramic and 4.7 µF to 10 µF, 35V tantalum capacitors. These

capacitors should be placed as close to power pins as prac-

tical and tightly connected to the power plane sandwich us-

ing multiple vias. Needless to say, multilayer board technol-

ogy should be employed for the CLC018 and similar high-

frequency-capability devices.

CONFIGURING THE SWITCH

The CLC018 can be configured so that any output may be in-

dependently connected to any input and any input be con-

nected to any or all outputs. Each output may be indepen-

dently enabled or placed in a high-impedance state.

Data controlling the switch matrix and output mode are

stored in two ranks of eight, 4-bit registers, one register per

output. The three most-significant bits in each register iden-

tify the input to be connected to that output. The least-

significant bit controls whether the output is active or

TRI-STATE. A particular register in the first rank, the LOAD

REGISTERS, is selected by a 3-bit word placed on the out-

DS100088-14

FIGURE 5. Single Ended Input to CLC018

DS100088-15

FIGURE 6. Single Ended Input to CLC018

DS100088-16

FIGURE 7. Generating 10k ECL Outputs

DS100088-17

FIGURE 8. Generating ECL Outputs

DS100088-18

FIGURE 9. Connecting the CLC018 to the CLC016

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