MSP430F133IPM datasheet(13/59 Pages) TI

13 / 59 page

MSP430x13x, MSP430x14x, MSP430x14x1

MIXED SIGNAL MICROCONTROLLER

SLAS272F − JULY 2000 − REVISED JUNE 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.

The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up

External Reset

Watchdog

Flash memory

WDTIFG

KEYV

(see Note 1)

Reset

0FFFEh

15, highest

NMI

Oscillator Fault

Flash memory access violation

NMIIFG (see Notes 1 & 4)

OFIFG (see Notes 1 & 4)

ACCVIFG (see Notes 1 & 4)

(Non)maskable

0FFFCh

Timer_B7 (see Note 5)

TBCCR0 CCIFG (see Note 2)

Maskable

0FFFAh

Timer_B7 (see Note 5)

TBCCR1 to 6 CCIFGs,

TBIFG (see Notes 1 & 2)

Maskable

0FFF8h

Comparator_A

CAIFG

Maskable

0FFF6h

Watchdog timer

WDTIFG

Maskable

0FFF4h

USART0 receive

URXIFG0

Maskable

0FFF2h

USART0 transmit

UTXIFG0

Maskable

0FFF0h

ADC12 (see Note 6)

ADC12IFG (see Notes 1 & 2)

Maskable

0FFEEh

Timer_A3

TACCR0 CCIFG (see Note 2)

Maskable

0FFECh

Timer_A3

TACCR1 CCIFG,

TACCR2 CCIFG,

TAIFG (see Notes 1 & 2)

Maskable

0FFEAh

I/O port P1 (eight flags)

P1IFG.0 to P1IFG.7

(see Notes 1 & 2)

Maskable

0FFE8h

USART1 receive

URXIFG1

Maskable

0FFE6h

USART1 transmit

UTXIFG1

0FFE4h

I/O port P2 (eight flags)

P2IFG.0 to P2IFG.7

(see Notes 1 & 2)

Maskable

0FFE2h

0FFE0h

0, lowest

NOTES:

1. Multiple source flags

2. Interrupt flags are located in the module.

3. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

4. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable

it.

5. Timer_B7 in MSP430x14x(1) family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs. In Timer_B3 there are only interrupt

flags TBCCR0, 1, and 2 CCIFGs and the interrupt-enable bits TBCCTL0, 1, and 2 CCIEs.

6. ADC12 is not implemented on the 14x1 devices.

MSP430F133IPM Datasheet(PDF) 13 Page - Texas Instruments

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