MICRF501 datasheet(16/18 Pages) MICREL

16 / 18 page

MICRF501

Micrel

MICRF501

March 2003

6. A new control word is entered into the first register. A

transition on the REGIN signal when CLKIN is high will

now turn the power amplifier off.

7. When the power amplifier is turned off an internal load

pulse is generated. The new control word is loaded into

the parallel register and the circuit enters a new mode

(in this case power down mode). CLKIN must go low

after the internal load pulse is generated.

As long as transitions on REGIN are avoided when CLKIN is

high, a new control word can be clocked into the first register

any time without affecting the operation of the transceiver.

Example 1. f

RF = 434.245MHz, frequency deviation:

≈ ±10kHz, f

XCO = 10.00MHz. FSK modulation is implemented

by switching between dividers.

127

115

143

106

RxFilt

Pa2

Pa1

Pa0

ByLNA

011110

Ref6

Ref5

Ref4

Ref3

Ref2

Ref1

000000

Ref0

Cpmp1 Cpmp0

Fc1

Fc0

OutS2

010010

OutS1

OutS0

Mod1

Mod0

001011

001001

Binary form: (MSB to the left):

Tx:

010010 001011 000001111111

000001110011 0001011110 0001010101

011110000000010010001011

Rx:

011011 011011 000010001111

000010001111 0001101010 0001101010

011110000000010010001001

When FSK modulation is implemented by switching between

the different dividers A, N and M values corresponding to the

receive frequency and both transmit frequencies have to be

found.

When FSK modulation is applied to the VCO the PLL is using

the dividers A1, N1 and M1. When Mod1 = 1 and Mod0 = 0

it is possible to switch between the different dividers in the

PLL. DATAIXO controls the switching. When DATAIXO = 0

the PLL uses dividers A0, N0 and M0. When DATAIXO = 1 the

PLL uses dividers A1, N1 and M1. Switching between the

different dividers can be used to implement FSK modulation.

The N, M and A values can be calculated from the formula:

32 N

XCO

×+

where f

C is the comparison frequency.

The 8bit control word is first read into a shift-register, and is

then loaded into a parallel register by a transition of the

REGIN signal (positive or negative) when the CLKIN signal is

high. The circuit then goes directly into the specified mode

(receive, transmit, etc.).

CLKIN

12 3

REGIN

LOAD_INT

PA_C

LOCKDET

Figure 10. Timing of CLKIN, REGIN and the Internal

LOAD_INT and PA_C Signals

1. The second last bit is clocked into the first shift register

(‘1’).

2. The last bit is clocked into the first shift register (‘1’).

3. A transition on the REGIN signal generates an internal

load pulse that loads the control word into the parallel

Tx-mode). The circuit stabilizes in the new mode.

4. When the clock signal goes low, the power amplifier

(PA) is turned on slowly in order to minimize spurious

components on the RF output signal. To be sure the

PLL is in lock before the PA is turned on, the PA should

be turned on after LOCKDET has been set.

The negative transition on the clock signal should come

a minimum time of one period of the comparison fre-

quency after the internal load pulse is generated.

5. The power amplifier is fully turned on.

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