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NBC12439FN Datasheet(PDF) 13 Page - ON Semiconductor

Part # NBC12439FN
Description  3.3 V/5 V Programmable PLL Synthesized Clock Generator
PDF  20 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NBC12439FN Datasheet(HTML) 13 Page - ON Semiconductor

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NBC12439
http://onsemi.com
13
Figure 7. Power Supply Filter
PLL_VCC
VCC
NBC12439
0.01
mF
22
mF
L=1000
mH
R=15
W
0.01
mF
3.3 V or
5.0 V
RS = 10-15 W
3.3 V or
5.0 V
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. Figure 7
shows a 1000
mH choke. This value choke will show a
significant impedance at 10 KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_VCC pin, a low DC resistance
inductor is required (less than 15
W). Generally, the
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.
The NBC12439 provides sub-nanosecond output edge
rates and therefore a good power supply bypassing scheme
is a must. Figure 8 shows a representative board layout for
the NBC12439. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 8 is the low impedance connections
between VCC and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective
capacitor resonances at frequencies adequate to supply the
instantaneous switching current for the NBC12439 outputs.
It is imperative that low inductance chip capacitors are used.
It is equally important that the board layout not introduce
any of the inductance saved by using the leadless capacitors.
Thin interconnect traces between the capacitor and the
power plane should be avoided and multiple large vias
should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.
Figure 8. PCB Board Layout for NBC12439 (28 PLCC)
C2
1
C3
R1
Xtal
C1
C1
R1 = 10-15
W
C1 = 0.01
mF
C2 = 22
mF
C3 = 0.1
mF
= VCC
= GND
= Via
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on-board oscillator. Note the provisions for
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.
Although the NBC12439 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL), there still
may be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise-related
problems in most designs.



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