PCA9515DP datasheet(4/11 Pages) PHILIPS

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Philips Semiconductors

Product data sheet

PCA9515

I2C-bus repeater

2004 Jun 24

APPLICATION INFORMATION

A typical application is shown in Figure 3. In this example, the

system master is running on a 3.3 V I2C-bus while the slave is

connected to a 5 V bus. Both buses run at 100 kHz unless the slave

bus is isolated and then the master bus can run at 400 kHz. Master

devices can be placed on either bus.

SW00867

BUS0

BUS

MASTER

400 kHz

SLAVE

100 kHz

PCA9515

SDA

SDA0

SDA

SCL

SCL0

SCL

BUS1

3.3 V

5 V

SDA1

SCL1

Figure 3. Typical application

The PCA9515 is 5 V tolerant so it does not require any additional

circuitry to translate between the different bus voltages.

When one side of the PCA9515 is pulled LOW by a device on the

I2C-bus, a CMOS hysteresis type input detects the falling edge and

causes an internal driver on the other side to turn on, thus causing

the other side to also go LOW. The side driven LOW by the

PCA9515 will typically be at VOL = 0.5 V.

In order to illustrate what would be seen in a typical application, refer

to Figures 4 and 5. If the bus master in Figure 3 were to write to the

slave through the PCA9515, we would see the waveform shown in

Figure 4 on Bus 0. This looks like a normal I2C transmission until the

falling edge of the 8th clock pulse. At that point, the master releases

the data line (SDA) while the slave pulls it LOW through the

PCA9515. Because the VOL of the PCA9515 is typically around

0.5 V, a step in the SDA will be seen. After the master has

transmitted the 9th clock pulse, the slave releases the data line.

9th CLOCK PULSE

VOL OF MASTER

VOL OF PCA9515

2 V/DIV

SW00866

Figure 4. Bus 0 waveform

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