PCA9515DP datasheet(2/11 Pages) PHILIPS

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Philips Semiconductors

Product data sheet

PCA9515

I2C-bus repeater

2004 Jun 24

DESCRIPTION

The PCA9515 is a BiCMOS integrated circuit intended for

application in I2C and SMBus systems.

While retaining all the operating modes and features of the I2C

system it permits extension of the I2C-bus by buffering both the data

(SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF.

The I2C-bus capacitance limit of 400 pF restricts the number of

devices and bus length. Using the PCA9515 enables the system

designer to isolate two halves of a bus, thus more devices or longer

length can be accommodated. It can also be used to run two buses,

one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus,

where the 100 kHz bus is isolated when 400 kHz operation of the

other is required.

Two or more PCA9515s cannot be put in series. The PCA9515

design does not allow this configuration. Since there is no direction

pin, slightly different “legal” low voltage levels are used to avoid

lock-up conditions between the input and the output. A “regular low”

applied at the input of a PCA9515 will be propagated as a “buffered

low” with a slightly higher value. When this “buffered low” is applied

to another PCA9515, PCA9516, or PCA9518 in series, the second

PCA9515, PCA9516, or PCA9518 will not recognize it as a “regular

low” and will not propagate it as a “buffered low” again. The

PCA9511/9513/9514 and PCA9512 cannot be used in series with

the PCA9515, PCA9516, or PCA9518 but can be used in series with

themselves since they use shifting instead of static offsets to avoid

lock-up conditions.

FEATURES

• 2 channel, bi-directional buffer

• I2C-bus and SMBus compatible

• Active-HIGH repeater enable input

• Open-drain input/outputs

• Lock-up free operation

• Supports arbitration and clock stretching across the repeater

• Accommodates standard mode and fast mode I2C devices and

multiple masters

• Powered-off high impedance I2C pins

• Operating supply voltage range of 3.0 V to 3.6 V

• 5.5 V tolerant I2C and enable pins

• 0 to 400 kHz clock frequency1

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115, and 1000 V CDM per

JESD22-C101.

• Latch-up testing is done to JEDEC Standard JESD78 which

exceeds 100 mA.

• Package offerings: SO and TSSOP

PIN CONFIGURATION

n.c.

GND

SDA0

SCL1

SDA1

VCC

SCL0

SU01322

Figure 1. Pin configuration

PIN DESCRIPTION

SYMBOL

FUNCTION

n.c.

No connection

SCL0

Serial clock bus 0

SDA0

Serial data bus 0

GND

Supply ground

Active high repeater enable input

SDA1

Serial data bus 1

SCL1

Serial clock bus 1

VCC

Supply power

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

8-pin plastic SO

–40

°C to +85 °C

PCA9515D

PCA9515

SOT96-1

8-pin plastic TSSOP

–40

°C to +85 °C

PCA9515DP

9515

SOT505-1

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.

The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.

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