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SED1565DBB Datasheet(PDF) 77 Page - Epson Company |
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SED1565DBB Datasheet(HTML) 77 Page - Epson Company |
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77 / 87 page  SED1565 Series EPSON 8–75 (VDD = 2.7 V to 4.5 V, Ta = –40 to 85 °C ) Item Signal Symbol Condition Rating Units Min Max Address hold time A0 tAH6 0— ns Address setup time tAW6 0— ns System cycle time A0 tCYC6 300 — ns Data setup time D0 to D7 tDS6 40 — ns Data hold time tDH6 15 — ns Access time tACC6 CL = 100 pF — 140 ns Output disable time tOH6 10 100 ns Enable H pulse Read E tEWHR 120 — ns time Write tEWHW 60 — ns Enable L pulse Read E tEWLR 60 — ns time Write tEWLW 60 — ns Table 30 (VDD = 1.8 V to 2.7 V, Ta = –40 to 85 °C ) Item Signal Symbol Condition Rating Units Min Max Address hold time A0 tAH6 0— ns Address setup time tAW6 0— ns System cycle time A0 tCYC6 1000 — ns Data setup time D0 to D7 tDS6 80 — ns Data hold time tDH6 30 — ns Access time tACC6 CL = 100 pF — 280 ns Output disable time tOH6 10 200 ns Enable H pulse Read E tEWHR 240 — ns time Write tEWHW 120 — ns Enable L pulse Read E tEWLR 120 — ns time Write tEWLW 120 — ns Table 31 *1 The input signal rise time and fall time ( tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, ( tr + tf) ≤ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≤ (tCYC6 – tEWLR – tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E. |
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