TDA9885TSSLASHV3 datasheet(16/56 Pages) PHILIPS

16 / 56 page

2003 Oct 02

Philips Semiconductors

Product speciﬁcation

I2C-bus controlled single and multistandard

alignment-free IF-PLL demodulators

TDA9885; TDA9886

Table 7

Automatic frequency control bits; note 1

Note

1. f0 is the nominal frequency of fVIF.

9.2

Write format

Table 8

I2C-bus write format (slave receives data); note 1

Note

1. The auto-increment of the subaddress stops if the subaddress is 3.

Table 9

Explanation of Table 8

BIT

fVIF

AFC4

AFC3

AFC2

AFC1

0111

≤ (f0 − 187.5 kHz)

0110

f0 − 162.5 kHz

0101

f0 − 137.5 kHz

0100

f0 − 112.5 kHz

0011

f0 − 87.5 kHz

0010

f0 − 62.5 kHz

0001

f0 − 37.5 kHz

0000

f0 − 12.5 kHz

1111

f0 + 12.5 kHz

1110

f0 + 37.5 kHz

1101

f0 + 62.5 kHz

1100

f0 + 87.5 kHz

1011

f0 + 112.5 kHz

1010

f0 + 137.5 kHz

1001

f0 + 162.5 kHz

1000

≥ (f

0 + 187.5 kHz)

BYTE 1

BYTE 2

BYTE 3

BYTE n

A6 to A0

R/W

A7 to A0

bits 7 to 0

slave address

subaddress

data 1

data n

SYMBOL

FUNCTION

START condition, generated by the master

Slave address

see Table 4

R/W = 0

write command, generated by the master

acknowledge bit, generated by the slave

Subaddress (SAD)

see Table 10

Data 1, data n

8-bit data words, transmitted by the master (see Tables 11, 12 and 14)

STOP condition

TDA9885TS/V3 Datasheet(PDF) 16 Page - NXP Semiconductors

TDA9885TS/V3 Datasheet(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL