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ZR36060PQC Datasheet(PDF) 33 Page - List of Unclassifed Manufacturers

Part # ZR36060PQC
Description  Integrated JPEG CODEC
PDF  46 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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Integrated JPEG CODEC
8.3 Video Registers
Video Control Register
Address 0x030
SyncMstr: The ZR36060 is the Master or Slave of the Video syncs.
0
- Slave of Video syncs
1
- Master of Video syncs
FIExt: Field detection by external pin or decoding from H/VSYNC.
0
- Field detection (even/odd) by latching HSYNC with VSYNC
1
- Detect even/odd via the dedicated FI pin
FIVedge: Defines the start of a video field at the leading or trailing edge of VSYNC
(affects the reset point for the vertical counters, the FI signal state change, the next
field search upon START, and DATERR assertion when VSYNC arrives before
end of field compression).
0
- Leading edge of VSYNC
1
- Trailing edge of VSYNC
FIDet: Detection/meaning of correct field (after FIExt parameter).
0
- ODD fields: FI is low, or VSYNC latches the HSYNC pulse
1
- ODD fields: FI is high, or VSYNC latches the middle of a line
Range: Defines the full-scale range of the video bus pixels data in decompres-
sion. Has no effect in compression.
0
- Pixel values are full-scale with 256 levels.
1
- Pixel values limited between [16,235] (per CCIR 60.)
Video8: Defines the video bus width.
0
- 16-bit video bus
1
- 8-bit video bus
Video Polarity Register
Address 0x031
VSPol: Polarity for the VSYNC signal (note that this parameter is totally indepen-
dent of the FIVedge parameter)
0
- Sync pulse is active low
1
- Sync pulse is active high
HSPol: Polarity for the HSYNC signal
0
- Sync pulse is active low
1
- Sync pulse is active high
FIPol: Polarity for the FIeld Identification signal
0
- ODD fields: FI is low
1
- ODD fields: FI is high
BLPol: Polarity for the BLANK signal
0
- BLANK area is active low
1
- BLANK area is active high
SImgPol: Polarity for the SUBIMG signal
0
- SUBIMG is low before SVStart, SHStart and after SVEnd, SHEnd
1
- SUBIMG is high before SVStart, SHStart and after SVEnd, SHEnd
PoePol: Polarity for the POE signal to permit floating (disabling) of the ZR36060
video bus during decompression:
0
- Disable bus when input is low
1
- Disable bus when input is high
PValPol: Polarity for the PVALID signal
0
- Pixels are valid when PVALID is low
1
- Pixels are valid when PVALID is high
VCLKPol: Polarity for the VCLK signal (used in 16-bit video width only)
0
- Pixels are valid when VCLK is low
1
- Pixels are valid when VCLK is high
Scaling Register
Address: 0x032
HScale: Horizontal down or up scaling (depending on compression/
decompression)
00b - No scaling
01b - 2:1 scaling ratio, with fixed horizontal filtering
10b - 4:1 scaling ratio, with fixed horizontal filtering
11b - Not used
VScale: Vertical down or up scaling (depending on compression/decompression)
0
- No scaling
1
- In compression, only even indexed lines (0,2,..) are processed. In decom-
pression, duplicate video lines
Background Color Registers
Address: 0x033 - 0x035
BackX: Y, U, V components for the background color (used only in
decompression)
0x030
7
6
5
4
3
2
1
0
Video8
R/W
X
default
type
Range
–
X
0
–
X
0
–
X
FIDet
R/W
X
FIVedge
R/W
X
FIExt
R/W
X
SyncMstr
R/W
0
0x031
7
6
5
4
3
2
1
0
VCLKPol
R/W
X
default
type
PValPol
R/W
X
PoePol
R/W
X
SImgPol
R/W
X
BLPol
R/W
X
FIPol
R/W
X
HSPol
R/W
X
VSPol
R/W
X
0x032
7
6
5
4
3
2
1
0
0
–
X
default
type
0
–
X
0
–
X
0
–
X
0
–
X
VScale
R/W
X
HScale
R/W
X
R/W
X
0x033
7
6
5
4
3
2
1
0
BackY[7:0]
R/W
X
default
type
0x034
BackU[7:0]
0x035
BackV[7:0]



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