COP688CL datasheet(24/40 Pages) NSC

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WATCHDOG Operation (Continued)

TABLE III WATCHDOG Service Actions

Key

Window

Clock

Action

Data

Monitor

Match

Valid Service Restart Service Window

Don’t Care

Mismatch

Don’t Care

Error Generate WATCHDOG Output

Mismatch

Don’t Care

Error Generate WATCHDOG Output

Don’t Care

Mismatch

Error Generate WATCHDOG Output

TABLE IV MICROWIREPLUS

Master Mode Clock Select

SL1

SL0

2 c tc

4 c tc

8 c tc

Where tc is the instruction cycle clock

The Clock Monitor forces the G1 pin low upon detecting a

clock frequency error The Clock Monitor error will continue

until the clock frequency has reached the minimum speci-

fied value after which the G1 output will enter the high im-

pedance TRI-STATE mode following 16 tc–32 tc clock cy-

cles The Clock Monitor generates a continual Clock Moni-

tor error if the oscillator fails to start or fails to reach the

minimum specified frequency The specification for the

Clock Monitor is as follows

1tc l 10 kHzNo clock rejection

1tc k 10 HzGuaranteed clock rejection

WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the WATCHDOG and

Clock Monitor should be noted

Both WATCHDOG and Clock Monitor detector circuits

are inhibited during reset

Following reset the WATCHDOG and Clock Monitor are

both enabled with the WATCHDOG having the maxi-

mum service window selected

The WATCHDOG service window and Clock Monitor en-

abledisable option can only be changed once during

the initial WATCHDOG service following reset

The initial WATCHDOG service must match the key data

value in the WATCHDOG Service register WDSVR in or-

der to avoid a WATCHDOG error

Subsequent WATCHDOG services must match all three

data fields in WDSVR in order to avoid WATCHDOG er-

rors

The correct key data value cannot be read from the

WATCHDOG Service register WDSVR Any attempt to

read this key data value of 01100 from WDSVR will read

as key data value of all 0’s

The WATCHDOG detector circuit is inhibited during both

the HALT and IDLE modes

The Clock Monitor detector circuit is active during both

the HALT and IDLE modes Consequently the device

inadvertently entering the HALT mode will be detected

as a Clock Monitor error (provided that the Clock Monitor

enable option has been selected by the program)

With the single-pin RC oscillator mask option selected

and the CLKDLY bit reset the WATCHDOG service win-

dow will resume following HALT mode from where it left

off before entering the HALT mode

With the crystal oscillator mask option selected or with

the single-pin RC oscillator mask option selected and

the CLKDLY bit set the WATCHDOG service window will

be set to its selected value from WDSVR following HALT

Consequently the WATCHDOG should not be serviced

for at least 2048 instruction cycles following HALT but

must be serviced within the selected window to avoid a

WATCHDOG error

The IDLE timer T0 is not initialized with reset

The user can sync in to the IDLE counter cycle with an

IDLE counter (T0) interrupt or by monitoring the T0PND

flag The T0PND flag is set whenever the thirteenth bit of

the IDLE counter toggles (every 4096 instruction cycles)

The user is responsible for resetting the T0PND flag

A hardware WATCHDOG service occurs just as the de-

vice exits the IDLE mode Consequently the Watchdog

should not be serviced for at least 2048 instruction cy-

cles following IDLE but must be serviced within the se-

lected window to avoid a WATCHDOG error

Following reset the initial WATCHDOG service (where

the service window and the Clock Monitor enabledis-

able must be selected) may be programmed anywhere

within the maximum service window (65536 instruction

cycles) initialized by RESET

Note that this initial

WATCHDOG service may be programmed within the ini-

tial 2048 instruction cycles without causing a WATCH-

DOG error

Detection of Illegal Conditions

The device can detect various illegal conditions resulting

from coding errors transient noise power supply voltage

drops runaway programs etc

Reading of undefined ROM gets zeros The opcode for soft-

ware interrupt is zero If the program fetches instructions

from undefined ROM this will force a software interrupt

thus signaling that an illegal condition has occurred

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