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COP688CL Datasheet(PDF) 30 Page - National Semiconductor (TI) |
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COP688CL Datasheet(HTML) 30 Page - National Semiconductor (TI) |
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30 / 40 page ![]() Instruction Execution Time Most instructions are single byte (with immediate address- ing mode instructions taking two bytes) Most single byte instructions take one cycle time to execute Skipped instructions require x number of cycles to be skipped where x equals the number of bytes in the skipped instruction opcode See the BYTES and CYCLES per INSTRUCTION table for details Bytes and Cycles per Instruction The following table shows the number of bytes and cycles for each instruction in the format of bytecycle Arithmetic and Logic Instructions B Direct Immed ADD 11 34 22 ADC 11 34 22 SUBC 11 34 22 AND 11 34 22 OR 11 34 22 XOR 11 34 22 IFEQ 11 34 22 IFNE 11 34 22 IFGT 11 34 22 IFBNE 11 DRSZ 13 SBIT 11 34 RBIT 11 34 IFBIT 11 34 RPND 11 Instructions UsingAC CLRA 11 INCA 11 DECA 11 LAID 13 DCOR 11 RRCA 11 RLCA 11 SWAPA 11 SC 11 RC 11 IFC 11 IFNC 11 PUSHA 13 POPA 13 ANDSZ 22 Transfer of Control Instructions JMPL 34 JMP 23 JP 13 JSRL 35 JSR 25 JID 13 VIS 15 RET 15 RETSK 15 RETI 15 INTR 17 NOP 11 Memory Transfer Instructions Register Direct Immed Register Indirect Indirect Auto Incr Decr B X Ba Bb Xa Xb XA 11 13 23 12 13 LD A 11 13 23 22 12 13 LD B Imm 11 (IF B k 16) LD B Imm 22 (IF B l 15) LD Mem Imm 22 33 22 LD Reg Imm 23 IFEQ MD Imm 33 e l Memory location addressed by B or X or directly http www nationalcom 30 |
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