74HC datasheet(18/19 Pages) PHILIPS

18 / 19 page

March 1988

Philips Semiconductors

HCMOS family characteristics

FAMILY SPECIFICATIONS

AC switching parameters

Input frequency; for combinatorial logic devices

the maximum number of inputs and outputs

switching in accordance with the device

function table. For sequential logic devices the

clock frequency using alternate HIGH and LOW

for data input or using the toggle mode,

whichever is applicable.

Output frequency; each output.

fmax

Maximum clock frequency; clock input

waveforms should have a 50% duty factor and

be such as to cause the outputs to be switching

from 10%VCC to 90%VCC in accordance with

the device function table.

Hold time; the interval immediately following the

active transition of the timing pulse (usually the

clock pulse) or following the transition of the

control input to its latching level, during which

interval the data to be recognized must be

maintained at the input to ensure their

continued recognition. A negative hold time

indicates that the correct logic level may be

released prior to the timing pulse and still be

recognized.

tr,

Clock input rise and fall times; 10% and 90%

values.

tPHL

Propagation delay; the time between the

speciﬁed reference points, normally the 50%

points for 74HC and 74HCU devices on the

input and output waveforms and the 1.3 V

points for the 74HCT devices, with the output

changing from the deﬁned HIGH level to the

deﬁned LOW level.

tPLH

Propagation delay; the time between the

speciﬁed reference points, normally the 50%

points for 74HC and 74HCU devices on the

input and output waveforms and the 1.3 V point

for the 74HCT devices, with the output

changing from the deﬁned LOW level to the

deﬁned HIGH level.

tPHZ

3-state output disable time; the time between

the speciﬁed reference points, normally the

50% points for the 74HC and 74HCU devices

and the 1.3 V points for the 74HCT devices on

the output enable input voltage waveform and a

point representing 10% of the output swing on

the output voltage waveform of a 3-state

device, with the output changing from

a HIGH level (VOH) to a high impedance

OFF-state (Z).

tPLZ

3-state output disable time; the time between

the speciﬁed reference points, normally the

50% points for the 74HC devices and the 1.3 V

points for the 74HCT devices on the output

enable input voltage waveform and a point

representing 10% of the output swing on the

output voltage waveform of a 3-state

device, with the output changing from a LOW

level (VOL) to a high impedance OFF-state (Z).

tPZH

3-state output enable time; the time between

the speciﬁed reference points, normally the

50% points for the 74HC devices and 1.3 V

points for the 74HCT devices on the output

enable input voltage waveform and the 50%

point on the output voltage waveform of a

3-state device, with the output changing from a

high impedance OFF-state (Z) to a HIGH level

(VOH).

tPZL

3-state output enable time; the time between

the speciﬁed reference points, normally the

50% points for the 74HC devices and the 1.3 V

points for the 74HCT devices on the output

enable input voltage waveform and the 50%

point on the output voltage waveform of a

3-state device, with the output changing from a

high impedance OFF-state (Z) to a LOW level

(VOL).

trem

Removal time; the time between the end of an

overriding asynchronous input, typically a clear

or reset input, and the earliest permissible

beginning of a synchronous control input,

typically a clock input, normally measured at

the 50% points for 74HC devices and the 1.3 V

points for the 74HCT devices on both input

voltage waveforms.

tsu

Set-up time; the interval immediately preceding

the active transition of the timing pulse (usually

the clock pulse) or preceding the transition of

the control input to its latching level, during

which interval the data to be recognized must

be maintained at the input to ensure their

recognition. A negative set-up time indicates

that the correct logic level may be initiated

sometime after the active transition of the

timing pulse and still be recognized.

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