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MAC7100CVF Datasheet(PDF) 14 Page - Motorola, Inc

Part # MAC7100CVF
Description  MAC7100 Microcontroller Family Hardware Specifications
PDF  48 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MAC7100CVF Datasheet(HTML) 14 Page - Motorola, Inc

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MAC7100 Microcontroller Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical Characteristics
3.8
Clock and Reset Generator Electrical
Characteristics
This section describes the electrical characteristics for the oscillator, phase-locked loop, clock monitor and
reset generator.
3.8.1
Oscillator Characteristics
The MAC7100 Family features an internal low power loop controlled Pierce oscillator and a full swing Pierce
oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce
oscillator/external clock depends on the level of the XCLKS signal at the rising edge of the RESET signal.
Before asserting the oscillator to the internal system clock distribution subsystem, the quality of the
oscillation is checked for each start from either power on, STOP or oscillator fail. tCQOUT specifies the
maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is
not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also
features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal
is below the Clock Monitor Assert Frequency fCMFA.
Table 17. Oscillator Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
H1a C Crystal oscillator range (loop controlled Pierce)
fOSC
4.0
—
16
MHz
H1b C Crystal oscillator range (full swing Pierce) 1, 2
1 Depending on the crystal; a damping series resistor might be necessary
2 XCLKS negated during reset
fOSC
0.5
—
40
MHz
H2
P Startup Current
IOSC
100
—
—
µA
H3
C Oscillator start-up time (loop controlled Pierce)
tUPOSC
—TBD 3
3 fosc = 4 MHz, C = 22 pF.
50 4
4 Maximum value is for extreme cases using high Q, low frequency crystals
ms
H4
D Clock Quality check time-out
tCQOUT
0.45
—
2.5
s
H5
P Clock Monitor Failure Assert Frequency
fCMFA
50
100
200
KHz
H6
P External square wave input frequency 2
fEXT
0.5
—
40
MHz
H7
D External square wave pulse width low
tEXTL
9.5
—
—
ns
H8
D External square wave pulse width high
tEXTH
9.5
—
—
ns
H9
D External square wave rise time
tEXTR
——
1
ns
H10 D External square wave fall time
tEXTF
——
1
ns
H11 D Input Capacitance (EXTAL, XTAL pins)
CIN
—7
—
pF
H12 C EXTAL pin DC Operating Bias in loop controlled
mode
VDCBIAS
—TBD
—
V
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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