TLV2370, TLV2371, TLV2372, TLV2373, TLV2374, TLV2375

FAMILY OF 550 µA/Ch 3MHz RAILTORAIL INPUT/OUTPUT

OPERATIONAL AMPLIFIERS WITH SHUTDOWN

SLOS270C − MARCH 2001 − REVISED DECEMBER 2003

14

WWW.TI.COM

POST OFFICE BOX 1443

APPLICATION INFORMATION

rail-to-rail input operation

The TLV237x input stage consists of two differential transistor pairs, NMOS and PMOS, that operate together

to achieve rail-to-rail input operation. The transition point between these two pairs can be seen in Figures 1,

2, and 3 for a 2.7-V, 5-V, and 15-V supply. As the common-mode input voltage approaches the positive supply

rail, the input pair switches from the PMOS differential pair to the NMOS differential pair. This transition occurs

approximately 1.35 V from the positive rail and results in a change in offset voltage due to different device

characteristics between the NMOS and PMOS pairs. If the input signal to the device is large enough to swing

between both rails, this transition results in a reduction in common-mode rejection ratio (CMRR). If the input

signal does not swing between both rails, it is best to bias the signal in the region where only one input pair is

active. This is the region in Figures 1 through 3 where the offset voltage varies slightly across the input range

and optimal CMRR can be achieved. This has the greatest impact when operating from a 2.7-V supply voltage.

driving a capacitive load

When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s

phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than

in Figure 33. A minimum value of 20

Ω should work well for most applications.

CLOAD

RF

Input

Output

RG

RNULL

+

−

VDD/2

Figure 33. Driving a Capacitive Load

offset voltage

the corresponding gains. The following schematic and formula can be used to calculate the output offset

voltage:

V

OO +

V

IO

1

)

R

F

R

G

" I

IB

)

R

S

1

)

R

F

R

G

" I

IB–

R

F

+

−

VI

+

RG

RS

RF

IIB−

VO

IIB+

Figure 34. Output Offset Voltage Model