AMC7812BSPAPR datasheet(49/92 Pages) TI1

49 / 92 page

AMC7812B

www.ti.com

SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013

POWER-SUPPLY SEQUENCE

The preferred (not required) order for applying power is IOVDD, DVDD/AVDD, and then AVCC. All registers

initialize to the default values after these supplies are established. Communication with the device is valid after a

250-µs maximum power-on reset delay. The default state of all analog blocks is off as determined by the power-

down register (6Bh). Before writing to this register, a hardware reset should be issued to ensure specified device

operation. Device communication is valid after a maximum 250-µs reset delay from the RESET rising edge. If

DVDD falls below 2.7 V, the minimum supply value of DVDD, either issue a hardware or power-on reset in order

to resume proper operation.

To avoid activating the device ESD protection diodes, do not apply the GPIO-4, GPIO-5, GPIO-6, and GPIO-7

inputs before the AVDD is established. Also, if using the external reference configuration of the ADC, do not

apply ADC-REF-IN/CMP before AVDD.

PRIMARY COMMUNICATION INTERFACE

The device communicates with the system controller through the primary communication interface, which can be

configured as either an I2C-compatible two-wire bus or an SPI bus. When the SPI/I2C pin is tied to ground, the

I2C interface is enabled and the SPI is disabled. When the SPI/I2C pin is tied to IOVDD, the I2C interface is

disabled and the SPI is enabled.

I2C-Compatible Interface

This device uses a two-wire serial interface compatible with the I2C-bus specification, version 2.1. The bus

consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and

SCL lines are pulled high. All I2C-compatible devices connect to the I2C bus through open-drain I/O pins SDA

and SCL. A master device, usually a microcontroller or a digital signal processor (DSP), controls the bus. The

master is responsible for generating the SCL signal and device addresses. The master also generates specific

conditions that indicate the start and stop of data transfers. A slave device receives and transmits data on the

bus under control of the master device. The AMC7812B functions as a slave and supports the following data

transfer modes, as defined in the I2C-bus specification: standard mode (100 kbps), fast mode (400 kbps), and

high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same;

therefore, they are referred to as F/S mode in this document. The protocol for high-speed mode is different from

the F/S mode, and is referred to as Hs mode. The device supports 7-bit addressing. However 10-bit addressing

and general-call addressing are not supported. The device slave address is determined by the status of pins A0,

A1, and A2, as shown in Table 8.

Table 8. Slave Addresses

SLAVE ADDRESS

GND

1100001

GND

IOVDD

0101100

GND

IOVDD

GND

1100100

GND

IOVDD

0101110

IOVDD

GND

1100010

IOVDD

GND

IOVDD

0101101

IOVDD

GND

1100101

IOVDD

0101111

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