DP8344B datasheet(23/184 Pages) NSC

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20 CPU Description (Continued)

Shift and Rotate Instructions

The shift and rotate instructions operate on any of the 8-bit

CPU registers The BCP supports shift left shift right and

rotate operations Table 2-8 lists the shift and rotate instruc-

tions

Comparison Instructions

The BCP utilizes two comparison instructions The CMP in-

struction performs a two’s complement subtraction between

a register and immediate data The BIT instruction tests se-

lected bits in a register by ANDing it with immediate data

Neither instruction stores its results only the ALU flags are

affected Table 2-9 lists both of the comparison instructions

Program Flow Instructions

The BCP has a wide array of program flow instructions un-

conditional jumps calls and returns conditional jumps

calls and returns relative or absolute instruction addressing

on jumps and calls a specialized register field decoding

jump and software interrupt capabilities These instructions

redirect program flow by changing the Program Counter

The unconditional jump instructions support both relative in-

struction addressing the (JuMP instruction) and absolute

instruction addressing (the Long JuMP instruction) using

the following addressing modes Immediate Register Abso-

lute and Indexed Table 2-10 lists the unconditional jump

instructions and their variations

The conditional jump instructions support both relative in-

struction addressing and absolute instruction addressing us-

ing the Immediate and Absolute addressing modes The

conditional relative jump instruction tests flags in the Condi-

tion Code Register

CCR

and the Transceiver Status

TSR

Two possible syntaxes are supported for

the conditional relative jump instruction see Table 2-11

Table 2-12 lists the various flags ‘‘f’’ that the conditional

JMP instruction can test and Table 2-13 lists the various

conditions ‘‘cc’’ that the Jcc instruction can test for Keep in

TABLE 2-8 Shift and Rotate Instructions

Syntax

Instruction Operation

Addressing Mode

SHL

Rsdb

SHR

Rsdb

ROT

Rsdb

Note

‘‘b’’ e the number of bit shiftsrotates to perform

TABLE 2-9 Comparison Instructions

Syntax

Instruction Operation

Addressing Mode

CMP

rs n

Limited Register

BIT

rs n

Limited Register

Note

logical AND operation

TABLE 2-10 Unconditional Jump Instructions

Syntax

Instruction Operation

Operand Range

Addressing Mode

JMP

PC a n (sign extended)

xPC

128 a127

Immediate

JMP

PC a Rs (sign extended)

xPC

128 a127

LJMP

xPC

0 64k

Absolute

LJMP

xPC

0 64k

Indexed

Note

PC e Program Counter contents initially points to instruction following jump

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