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THEORY OF OPERATION

General Description

Digital-to-Analog Sections

R

R

12−Bit R−2R Ladder

Four MSBs Decoded into

15 Equal Segments

2R

2R

2R

2R

S0

S1

S11

2R

V

OUT

E15

2R

E2

2R

E1

V

REF

Output Range

DAC8830-EP

DAC8831-EP

SGLS334C – AUGUST 2006 – REVISED APRIL 2007

The DAC8830 and DAC8831 are single, 16-bit, serial-input, voltage-output DACs. They operate from a single

supply ranging from 2.7 V to 5 V, and typically consume 5

μA. Data is written to these devices in a 16-bit word

format, via an SPI serial interface. To ensure a known power-up state, these parts were designed with a

power-on reset function. The DAC8830 and DAC8831 are reset to zero code. In unipolar mode, the DAC8830

for the reference and analog ground are included on the DAC8831.

The DAC architecture for both devices consists of two matched DAC sections and is segmented. A simplified

circuit diagram is shown in Figure 45. The four MSBs of the 16-bit data word are decoded to drive 15 switches,

12 bits of the data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.

Figure 45. DAC Architecture

The output of the DAC is

Where:

Code = Decimal data word loaded to the DAC latch

17

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