DAC7642VF datasheet(12/25 Pages) TI1

12 / 25 page

DAC7642, DAC7643

SBAS233

www.ti.com

THEORY OF OPERATION

The DAC7642 and DAC7643 are dual channel, voltage

output, 16-bit DACs. The architecture is an R-2R ladder

configuration with the three MSB’s segmented followed by an

operational amplifier that serves as a buffer. Each DAC has

its own R-2R ladder network, segmented MSBs, and output

op amp, as shown in Figure 1. The minimum voltage output

(zero-scale) and maximum voltage output (full-scale) are set

by the external voltage references VREFL and VREFH, respec-

tively. The digital input is a 16-bit parallel word and the DAC

input registers offer a readback capability. The converters

can be powered from either a single +5V supply or a dual

±5V supply. Each device offers a reset function which imme-

diately sets all DAC output voltages, DAC registers and Input

registers to mid-scale, code 8000H (DAC7642), or to zero-

scale, code 0000H (DAC7643). See Figures 2 and 3 for the

basic configurations of the DAC7642 and DAC7643.

FIGURE 1. DAC7642 and DAC7643 Architecture.

REFH

OUT

OUT Sense

REFH Sense

REFL

REFL Sense

TYPICAL CHARACTERISTICS: VSS = –5V (Cont.)

At TA = +25°C, VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified.

Time (1

µs/div)

OUTPUT VOLTAGE

vs MIDSCALE GLITCH PERFORMANCE

+5V

LDAC

7FFF

H to 8000H

Time (1

µs/div)

OUTPUT VOLTAGE

vs MIDSCALE GLITCH PERFORMANCE

+5V

LDAC

8000

H to 7FFFH

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