1

2

3

4

12

11

10

9

V

IN

IN

VBB

V

Y0

Y0

V

CDCM1802

www.ti.com

SCAS759B – APRIL 2004 – REVISED NOVEMBER 2015

5 Pin Configuration and Functions

RGT Package

16-Pin VQFN

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

ENABLE. Enables or disables all outputs simultaneously; The EN pin offers three different

I

configurations: tie to GND (logic 0), external 60-k

EN

16

(with 60-k

Ω

according to S0 and S1 setting EN = 0; outputs Y[1:0] off (high-impedance); see Table 1 for

pullup)

details.

IN

2

Differential input clock. Input stage is sensitive and has a wide common mode range.

Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS, CML,

HSTL). Since the input is high-impedance, it is recommended to terminate the PCB

transmission line before the input (for example, with 100-

Ω across input). The input can also

I

be driven by a single-ended signal, if the complementary input is tied to a dc reference

Differential input

IN

3

The inputs deploy an ESD structure protecting the inputs in case of an input voltage

exceeding the rails by more than

≈0.7 V. Reverse biasing of the IC through this inputs is

possible and must be prevented by limiting the input voltage < VDD.

S0

13

I

Select mode of operation. Defines the output configuration of Y0 and Y1. Each pin offers

I

three different configurations: tied to GND (logic 0), external 60-k

Ω pulldown resistor (pull to

S1

15

(with 60-k

Ω

pullup)

LVCMOS clock output. This output provides a copy of IN or a divided down copy of clock IN

Y1

7

O

based on the selected mode of operation: S0, S1, and EN. Also, this output can be disabled

Y0

10

LVPECL clock output. This output provides a copy of IN or a divided down copy of clock IN

O

based on the selected mode of operation: S1, S0, and EN. If Y0 output is unused, the output

LVPECL

Y0

11

can simply be left open to save power and minimize noise impact to Y1.

Output bias voltage used to bias unused complementary input IN for single-ended input

VBB

4

O

drive is limited to about 1.5 mA.

(1)

1

Supply

Supply voltage PECL input + internal logic

PECL output supply voltage for output Y0;

(1)

9, 12

Supply

Caution: In this mode no voltage from outside may be forced because internal diodes could

be forced in a forward direction. Thus, it is recommended to leave the output disconnected.

Caution: In this mode no voltage from outside may be forced, because internal diodes could

8

Supply

be forced in forward direction. Thus, it is recommended to leave Y1 unconnected, tied to

GND, or terminated into GND.

5, 6, 14

Supply

Device ground

(1)

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