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DP83932B Datasheet(PDF) 47 Page - National Semiconductor (TI) |
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DP83932B Datasheet(HTML) 47 Page - National Semiconductor (TI) |
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47 / 96 page ![]() 50 Bus Interface (Continued) TABLE 5-1 Pin Description (Continued) Symbol Driver Direction Description Type NETWORK INTERFACE PINS (Continued) LBK TP O This pin will be TRI-STATE until the DCR has been written to (See Section 432 EXUSR2 TRI O Z EXBUS for more information) Loopback (LBK) When ENDEC loopback is programmed this pin is asserted high Although this signal is used internally by the SONIC-16 it is also provided as an output to the user Extended User Output (EXUSR2) When EXBUS has been set (see Section 432) this pin becomes a programmable output It will remain TRI-STATE until the SONIC-16 becomes a bus master at which time it will be driven according to the value programmed in the DCR2 (Section 437) PCOMP TRI O Z Packet Compression This pin is used with the Management Bus of the DP83950 Repeater Interface Controller (RIC) The SONIC-16 can be programmed to assert PCOMP whenever there is a CAM match or when there is not a match The RIC uses this signal to compress (shorten) a received packet for management purposes and to reduce memory usage (See the DP83950 datasheet for more details on the RIC Management Bus) The operation of this pin is controlled by bits 1 and 2 in the DCR2 register PCOMP will remain TRI-STATE until these bits are written to SEL I Mode Select (EXT e 0) This pin is used to determine the voltage relationship between TXa and TXb during idle at the primary of the isolation transformer on the network interface When tied to VCC TXa and TXb are at equal voltages during idle When tied to ground the voltage at TXa is positive with respect to TXb during idle on the primary side of the isolation transformer ( Figure 6-2 ) PREJ I O Packet Reject This signal is used to reject received packets When asserted low for at least two receive clocks (RXC) the SONIC-16 will reject the incoming packet This pin can be asserted up to the 2nd to the last bit of reception to reject a packet X1 TP I Crystal or External Oscillator Input This signal is used to provide clocking signals for the internal ENDEC A crystal can be connected to this pin along with X2 or an oscillator module may be used Typically the output of an oscillator module is connected to this pin See Section 613 for more information about using oscillators or crystals X2 I O Crystal Feedback Output This signal is used to provide clocking signals for the internal ENDEC A crystal may be connected to this pin along with X1 or an oscillator module may be used See Section 613 for more information about using oscillator modules or crystals BUS INTERFACE PINS BMODE I Bus Mode This input enables the SONIC-16 to be compatible with standard microprocessor buses The level of this pin affects byte ordering (little or big endian) and controls the operation of the bus interface control signals A high level (tied to VCC) selects Motorola mode (big endian) and a low level (tied to ground) selects National Intel mode (little endian) Note the alternate pin definitions for AS ADS MRW MWR INT INT BR HOLD BG HLDA SRW SWR DSACK0 RDYi and DSACK1 RDYo When BMODE e 1 the first pin definition is used and when BMODE e 0 the second pin definition is used See Sections 541 544 and 545 D31 – D0 TRI I O Z Data Bus These bidirectional lines are used to transfer data on the system bus When the SONIC-16 is a bus master 16-bit data is transferred on D15 – D0 and 32-bit data is transferred on D31 – D0 When the SONIC-16 is accessed as a slave register data is driven onto lines D15 – D0 47 |
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