AT94K datasheet(4/192 Pages) ATMEL

4 / 192 page

AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02

The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by executing

powerful instructions in a single-clock cycle, and allows system designers to optimize power

consumption versus processing speed. The AVR core is based on an enhanced RISC archi-

tecture that combines a rich instruction set with 32 general-purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code-efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers at the same clock frequency. The AVR executes out of on-

chip SRAM. Both the FPGA configuration SRAM and the AVR instruction code SRAM can be

automatically loaded at system power-up using Atmel’s in-system programmable (ISP) AT17

Series EEPROM Configuration Memories.

State-of-the-art FPSLIC design tools, System Designer

™, were developed in conjunction with

the FPSLIC architecture to help reduce overall time-to-market by integrating microcontroller

development and debug, FPGA development and Place and Route, and complete system

co-verification in one easy-to-use software tool.

AT94K Datasheet(PDF) 4 Page - ATMEL Corporation