SGND

D2

EN

A2

A3

B3

C3

D3

A1

B1

C1

D1

VDD

PVIN

SW

PGND

FB

EAOUT

EANEG

SYNC/

MODE

SGND

D2

VDD

PVIN

SW

PGND

FB

EAOUT

EANEG

SYNC/

MODE

EN

A1

B1

C1

D1

A3

B3

C3

D3

A2

10PH

PWM/PFM

FB

EN

VDD

PVIN

EAOUT

EANEG SGND PGND

SW

ON/OFF

22.1k

680pF

22PF

VIN

2.8V to

5.5V

SYNC/

MODE

LM2619

V OU T

1.5V

10PF

LM2619

SNVS212B – NOVEMBER 2002 – REVISED MAY 2013

www.ti.com

Figure 3. Typical Circuit for 1.5-V Output Voltage

Connection Diagrams

10-Bump DSBGA Package

Figure 4. YPA Package Top View

Figure 5. YPA Package Bottom View

Pin Functions

Table 1. Pin Description

Pin No.

Pin Name

Function

A1

FB

Feedback Analog Input.

B1

EANEG

Inverting input of error amplifier.

C1

EAOUT

Output of error amplifier.

D1

SYNC/MODE

Synchronization Input. Use this digital input for frequency selection or modulation control. Set:

SYNC/MODE = high for low-noise 600kHz PWM mode

SYNC/MODE = low for low-current PFM mode

SYNC/MODE = a 500kHz–1MHz external clock for synchronization in PWM mode. (See OPERATING

MODE SELECTION and FREQUENCY SYNCHRONIZATION in Device Information.)

D2

EN

Enable Input. Set this Schmitt trigger digital input high for normal operation. For shutdown, set low. Set

EN low during system power-up and other low supply voltage conditions. (See SHUTDOWN MODE in

Device Information.)

D3

PGND

Power Ground.

C3

SW

Switching Node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an

inductor with a saturation current rating that exceeds the max Switch Peak Current Limit of the LM2619.

B3

PVIN

Power Supply Voltage Input to the internal PFET switch. Connect to the input filter capacitor.

A3

VDD

Analog Supply Input. If board layout is not optimum, an optional 0.1µF ceramic capacitor is suggested.

A2

SGND

Analog and Control Ground.

2

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