SA8028 datasheet(2/28 Pages) PHILIPS

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Philips Semiconductors

Product data

SA8028

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

2002 Feb 22

853-2277 27777

GENERAL DESCRIPTION

The SA8028 BICMOS device integrates programmable dividers,

charge pumps and phase comparators to implement phase–locked

loops. The device is designed to operate from 3 NiCd cells, in

pocket phones, with low current and nominal 3 V supplies.

The synthesizer operates at VCO input frequencies up to 2.5 GHz.

The synthesizer has fully programmable RF, IF, and reference

dividers. All divider ratios are supplied via a 3-wire serial

programming bus. The RF divider is a fractional-N divider with

programmable integer ratios from 33 to 509 and a fractional

resolution of 22 programmable bits (23 bits internal). A 2nd order

sigma-delta modulator is used to achieve fractional division.

Separate power and ground pins are provided to the charge pumps

and digital circuits. VDDCP must be equal to or greater than VDD.

The ground pins should be externally connected to prevent large

currents from flowing across the die and thus causing damage.

The charge pump current (gain) is fully programmable, while ISET is

set by an external resistance at the RSET pin (refer to section 1.5,

RF and IF Charge Pumps). The phase/frequency detector charge

pump outputs allow for implementing a passive loop filter.

FEATURES

• Extremely low phase noise:

L(f) = –101 dBc/Hz at 5 kHz offset at 800 MHz

• Low power

• Programmable Normal & Integral charge pump outputs:

Maximum output = 10.4 mA

• Digital fractional spurious compensation

• Hardware and software power-down

• I

DDsleep < 0.1 µA (typ) at VDD = 3.0 V

• Seperate supply for V

DD and VDDCP

• Programmable loop filter bandwidth

APPLICATIONS

• 500 to 2500 MHz wireless equipment

• Cellular phones, all standards including:

CDMA

: IS95-B,C WCDMA

: WCDMA / UMTS

GSM

: EDGE / GPRS

TDMA

: IS136 and EDGE

GAIT

: GSM and TDMA

• WLAN

• Wireless PDAs

• Satellite tuners and all other high frequency equipment

• Extreme fine frequency resolution applications

TOP VIEW

CLOCK

REFin+

REFin–

SR02176

N/C

VDDPre

GND

GNDPre

RFin+

RFin–

GNDCP

VDDCP

RSET

Figure 1.

HBCC24 pin configuration.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SA8028W

HBCC24

Plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm (CSP package)

SOT564-1

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