TMS320VC5509 datasheet(3/122 Pages) TI

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Revision History

April 2001 − Revised September 2004

SPRS163G

REVISION HISTORY

This revision history highlights the technical changes made to SPRS163F to generate SPRS163G.

Scope: Deleted Section 6.1 (Ball Grid Array Mechanical Data) and Section 6.2 (Low-Profile Quad Flatpack

Mechanical Data). Mechanical drawings of the 179-terminal GHH package and the 144-pin PGE package will be

appended to this document via an automated process.

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

Table 2−3, Signal Descriptions:

− updated FUNCTION column of McBSP2.FSX:

− changed “McBSP1.FSX is selected when the External Bus Selection Register has 00 in ...” to “McBSP2.FSX is

selected when the External Bus Selection Register has 00 in ...”

Section 3.3, Direct Memory Access (DMA) Controller:

− updated “The 5509 DMA controller allows transfers to be synchronized ...” paragraph:

− changed “The 5509 supports 21 separate sync events ...” to “The 5509 supports 19 separate sync events ...”

Table 3−33, USB Module Registers:

− deleted 0x67A0 row (HOSTCTL, Host DMA Control Register)

− deleted 0x67A1 row (HOSTEP, Host DMA Endpoint Register)

− deleted 0x67A2 row (HOST, Host DMA Status)

Figure 3−17, IFR0 and IER0 Bit Locations:

− added reset values

Section 3.10.3.1, Waking Up From IDLE With Oscillator Disabled:

− updated title of SPRA078

Section 4, Documentation Support:

− added “Disabling the Internal Oscillator on the TMS320VC5507/5509/5509A DSP application report (literature

number SPRA078)”

Updated Section 4.1, Device and Development-Support Tool Nomenclature

Section 5.6.1, Internal System Oscillator With External Crystal:

− “The internal oscillator is always enabled following a device reset ...” paragraph:

− changed “The oscillator requires an external crystal or ceramic resonator connected across the X1 and X2/CLKIN

pins.” to “The oscillator requires an external crystal connected across the X1 and X2/CLKIN pins.”

Table 5−25, McBSP Transmit and Receive Timing Requirements:

− updated footnote about “P” value

Table 5−26, McBSP Transmit and Receive Switching Characteristics:

− updated footnote about “P” value

101

Table 5−27, McBSP General-Purpose I/O Timing Requirements:

− updated footnote about “P” value

102

Table 5−29, McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0):

− updated footnote about “P” value

TMS320VC5509 Datasheet(PDF) 3 Page - Texas Instruments

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