Pin

Description

TTL LEVEL LOGIC PINS

(Continued)

11

ENCODED READ DATA OUTPUT (ERDO)

This output issues the raw pulsed output of the pulse detector when

enabled by the control register bits ERD0 and ERD1 (Bank (11) bits 3 and 4) When disabled (see Table III) this output

will be high When enabled the pulsed data from the pulse detector can continue to be issued to the synchronizer

depending on the combination of states of the ERD0 and ERD1 control register bits When both the ERD0 and ERD1

control register bits are high the part is put into a test mode where the gain of the GCA is held constant (ie fixed gain

mode) In this test mode the synchronizer and synthesizer VCOs can be driven by external test signals

12

ENCODED READ DATA INPUT (ERDIN)

This pin is the input to the synchronizer It is enableddisabled via control

register bits ERD0 and ERD1 (Bank (11) bits 2 and 3) When enabled (see Table III) this buffer admits external pulsed

data to the synchronizer via this pin and raw data output from the pulse detector is NOT internally fed to the

synchronizer This allows for testingexercising of the synchronizer or for external processing of the peak-detected

data prior to being fed to the synchronizer When ERDO is disabled the pulse detector’s data is fed internally to the

synchronizer When both the ERD0 and ERD1 control register bits are high the part is put into a test mode where the

gain controlled amplifier is put into a fixed gain In this test mode the synchronizer and synthesizer VCOs can be driven

by external test signals

14

SYNCHRONIZED DATA OUTPUT (SDO)

This output issues resynchronized data directly from the synchronizing PLL

block

15

MULTIPLEXED SYNCHRONIZED CLOCK OUTPUT (SCLK)

This output issues either the synchronizer or synthesizer

clock signal dependent on whether the device is in the read or non-read mode The synchronizer clock is selected

during read mode while the synthesizer clock is selected during non-read mode Multiplexing is done without glitches

19

CRYSTAL INPUT (XTLIN)

This input is the synthesizer and filter reference frequency input It is designed for

connection from a TTL frequency source Duty cycle is not critical An input attenuation resistor is normally used to

minimize transient noise at this pin

21

POLARITY OUTPUT (POLOUT)

This TTL output issues a signal that is the output of the pulse detector’s comparator

with hysteresis The logical polarity of this signal corresponds to the polarity of the signal at the channel input pins

22

SYNTHESIZER REFERENCE OUTPUT (SYNTH)

This output issues a continuous reference signal from the frequency

a bit in the control register (ENSTHO Bank (10) bit 5) The output frequency will be the same as the media code clock

rate

23

CONTROL REGISTER DATA OUTPUT (CRDO)

This output issues data from the control register It can be connected

to the input of another device’s control register such as the DP84900 (ENDEC) so that the number of data lines from

the controller can be minimized

27–30

SERVO SWITCH INPUTS

1

2

3

4 (S1 S2 S3 S4)

These pins in conjunction with the AGC HOLD pin

control the gating action of the gated servo peak detectors and the discharge of the servo channeIs These pins also

enabIe or disabIe the output internal signals the track follow and the seek modes according to Table IV

31

SERVO FIELD SELECT INPUT (SFIELD)

When at a high logic level this pin switches the hysteresis threshold control

of the puIse detector’s comparator from the SET HYSTERESIS-DATA FIELD (SETHYSD) pin to the SET

HYSTERESIS-SERVO FIELD (SETHYSS) pin It also switches the AGC controI from the AGC control capacitor-data

field (VAGCIND) pin to the AGC control capacitor-servo field (VAGCINS) pin When enabled by a control register bit

filter between data equalization control bits (EQ0 EQ1 EQ2 Bank (00) bits 9 10 11) and servo equalization control

bits (SERVO

EQ0 SERVO

EQ1 SERVO

EQ2 Bank (11) bits 10 11 12)

36

OPTICAL

The optical (unipolar) mode is enabled by the application of ground to this pin For magnetic operation this

pin must be left open (no connection to it) Refer to design guide for details of operation

67

COASTAGC HOLD INPUT (HOLD)

When high this input controls an internal switch which freezes the pulse detector

AGC level for the reading of the servo burst Phase comparisons within the synchronizer (read mode only) are also

disabled allowing the PLL to coast

77

CHARGE PUMP GAIN INPUT (CPGAIN)

This input selects the gain of the synchronizer’s charge pump in conjunction

with a bit in the control register (CPRATIO Bank (10) bit 12) (see Table VIII)

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